The following files were generated for 'adder' in directory
G:\Work\FPGA_CD\chapter4\exp4_1\ipcore_dir\

Generate XCO file:
   CORE Generator input file containing the parameters used to regenerate a
   core.

   * adder.xco

Generate Implementation Netlist:
   Binary Xilinx implementation netlist files containing the information
   required to implement the module in a Xilinx (R) FPGA.

   * adder.ngc

Generate Instantiation Templates:
   Template files containing code that can be used as a model for instantiating
   a CORE Generator module in a VHDL design.

   * adder.veo

RTL Simulation Model Generator:
   Please see the core data sheet.

   * adder.v

All Documents Generator:
   Please see the core data sheet.

   * adder/doc/c_addsub_v11_0_vinfo.html
   * adder/doc/ds214_addsub.pdf

Deliver IP Symbol:
   Graphical symbol information file. Used by the ISE tools and some third party
   tools to create a symbol representing the core.

   * adder.asy

SYM file generator:
   Generate a SYM file for compatibility with legacy flows

   * adder.sym

Generate XMDF file:
   ISE Project Navigator interface file. ISE uses this file to determine how the
   files output by CORE Generator for the core can be integrated into your ISE
   project.

   * adder_xmdf.tcl

Generate ISE project file:
   ISE Project Navigator support files. These are generated files and should not
   be edited directly.

   * adder.gise
   * adder.xise

Deliver Readme:
   Text file indicating the files generated and how they are used.

   * adder_readme.txt

Generate FLIST file:
   Text file listing all of the output files produced when a customized core was
   generated in the CORE Generator.

   * adder_flist.txt

Please see the Xilinx CORE Generator online help for further details on
generated files and how to use them.

