##############################################################
#
# Xilinx Core Generator version 13.2
# Date: Sun May 06 10:16:29 2012
#
##############################################################
#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
#  Generated from component: xilinx.com:ip:c_addsub:11.0
#
##############################################################
#
# BEGIN Project Options
SET addpads = false
SET asysymbol = true
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = false
SET designentry = Verilog
SET device = xc6slx9
SET devicefamily = spartan6
SET flowvendor = Other
SET formalverification = false
SET foundationsym = false
SET implementationfiletype = Ngc
SET package = tqg144
SET removerpms = false
SET simulationfiles = Behavioral
SET speedgrade = -3
SET verilogsim = true
SET vhdlsim = false
# END Project Options
# BEGIN Select
SELECT Adder_Subtracter xilinx.com:ip:c_addsub:11.0
# END Select
# BEGIN Parameters
CSET a_type=Signed
CSET a_width=8
CSET add_mode=Add
CSET ainit_value=0
CSET b_constant=false
CSET b_type=Signed
CSET b_value=00000000
CSET b_width=8
CSET borrow_sense=Active_Low
CSET bypass=false
CSET bypass_ce_priority=CE_Overrides_Bypass
CSET bypass_sense=Active_High
CSET c_in=false
CSET c_out=false
CSET ce=true
CSET component_name=adder
CSET implementation=Fabric
CSET latency=1
CSET latency_configuration=Manual
CSET out_width=8
CSET sclr=false
CSET sinit=false
CSET sinit_value=0
CSET sset=false
CSET sync_ce_priority=Sync_Overrides_CE
CSET sync_ctrl_priority=Reset_Overrides_Set
# END Parameters
# BEGIN Extra information
MISC pkg_timestamp=2011-06-21T06:26:48.000Z
# END Extra information
GENERATE
# CRC: 766032c6
