CoreGen has not been configured with any user repositories.
CoreGen has been configured with the following Xilinx repositories:
 - 'G:\Software\ISE_DS\ISE\coregen\' [using existing xil_index.xml]
INFO:encore:314 - Created non-GUI application for batch mode execution.
Wrote CGP file for project 'coregen'.
INFO:sim - Generating component instance 'ila_pro_0' of
   'xilinx.com:ip:chipscope_ila:1.04.a' from
   'G:\Software\ISE_DS\ISE\coregen\iprepo\Chipscope\pcores\chipscope_ila_v1_04_a
   \chipscope_ila_v1_04_a.xcd'.
Resolving generic values...
Finished resolving generic values.
Generating IP...
Gathering HDL files for ila_pro_0 root...
Creating XST project for ila_pro_0...
Creating XST script file for ila_pro_0...
Creating XST instantiation file for ila_pro_0...
Running XST for ila_pro_0...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Generating VHDL wrapper
Not generating Verilog wrapper
Creating ISE instantiation template for ila_pro_0...
Skipping Verilog instantiation template for ila_pro_0...
Finished Generation.
Generating IP instantiation template...
Generating metadata file...
Generating ISE project...
Generating README file...
Generating FLIST file...
INFO:sim - Finished FLIST file generation.
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.
