Running: G:\Software\ISE_DS\ISE\bin\nt64\unwrapped\fuse.exe -intstyle ise -incremental -lib unisims_ver -lib unimacro_ver -lib xilinxcorelib_ver -lib secureip -o G:/Work/Xilinx/LX9/exp4_2/tb_test_isim_beh.exe -prj G:/Work/Xilinx/LX9/exp4_2/tb_test_beh.prj work.tb_test work.glbl 
ISim O.61xd (signature 0x1cce1bb2)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 
Determining compilation order of HDL files
Analyzing Verilog file \"G:/Work/Xilinx/LX9/exp4_2/test.v\" into library work
Analyzing Verilog file \"G:/Work/Xilinx/LX9/exp4_2/tb_test.v\" into library work
Analyzing Verilog file \"G:/Software/ISE_DS/ISE//verilog/src/glbl.v\" into library work
Starting static elaboration
Completed static elaboration
Compiling module test
Compiling module tb_test
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 3 Verilog Units
Built simulation executable G:/Work/Xilinx/LX9/exp4_2/tb_test_isim_beh.exe
Fuse Memory Usage: 16868 KB
Fuse CPU Usage: 202 ms
