Release 13.2 - xst O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.29 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 1.00 secs
Total CPU time to Xst completion: 0.29 secs
 
--> Reading design: zhongzhilvbo.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "zhongzhilvbo.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "zhongzhilvbo"
Output Format                      : NGC
Target Device                      : xc6slx9-3-tqg144

---- Source Options
Top Module Name                    : zhongzhilvbo
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file \"G:\Work\FPGA_CD\chapter4\exp4_7\Midian_fpga\zhongzhilvbo\compare8.v\" into library work
Parsing module <compare8>.
Analyzing Verilog file \"G:\Work\FPGA_CD\chapter4\exp4_7\Midian_fpga\zhongzhilvbo\uutcompare8.v\" into library work
Parsing module <uutcompare8>.
Analyzing Verilog file \"G:\Work\FPGA_CD\chapter4\exp4_7\Midian_fpga\zhongzhilvbo\zhongzhilvbo.v\" into library work
Parsing module <zhongzhilvbo>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <zhongzhilvbo>.

Elaborating module <uutcompare8>.

Elaborating module <compare8>.
WARNING:HDLCompiler:1499 - "G:\Work\FPGA_CD\chapter4\exp4_7\Midian_fpga\zhongzhilvbo\compare8.v" Line 35: Empty module <compare8> remains a black box.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <zhongzhilvbo>.
    Related source file is "g:/work/fpga_cd/chapter4/exp4_7/midian_fpga/zhongzhilvbo/zhongzhilvbo.v".
    Found 8-bit register for signal <dtm12>.
    Found 8-bit register for signal <dtm13>.
    Found 8-bit register for signal <dtm21>.
    Found 8-bit register for signal <dtm22>.
    Found 8-bit register for signal <dtm23>.
    Found 8-bit register for signal <dtm31>.
    Found 8-bit register for signal <dtm32>.
    Found 8-bit register for signal <dtm33>.
    Found 8-bit register for signal <dtm221>.
    Found 8-bit register for signal <dtm222>.
    Found 8-bit register for signal <dtm223>.
    Found 8-bit register for signal <dout>.
    Found 8-bit register for signal <dtm11>.
    Summary:
	inferred 104 D-type flip-flop(s).
	inferred  45 Multiplexer(s).
Unit <zhongzhilvbo> synthesized.

Synthesizing Unit <uutcompare8>.
    Related source file is "g:/work/fpga_cd/chapter4/exp4_7/midian_fpga/zhongzhilvbo/uutcompare8.v".
    Summary:
	no macro.
Unit <uutcompare8> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 13
 8-bit register                                        : 13
# Multiplexers                                         : 45
 8-bit 2-to-1 multiplexer                              : 45

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 104
 Flip-Flops                                            : 104
# Multiplexers                                         : 45
 8-bit 2-to-1 multiplexer                              : 45

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <zhongzhilvbo> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block zhongzhilvbo, actual ratio is 3.

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 104
 Flip-Flops                                            : 104

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : zhongzhilvbo.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 105
#      INV                         : 1
#      LUT6                        : 104
# FlipFlops/Latches                : 104
#      FDR                         : 104
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 81
#      IBUF                        : 73
#      OBUF                        : 8
# Others                           : 21
#      compare8                    : 21

Device utilization summary:
---------------------------

Selected Device : 6slx9tqg144-3 


Slice Logic Utilization: 
 Number of Slice Registers:             104  out of  11440     0%  
 Number of Slice LUTs:                  105  out of   5720     1%  
    Number used as Logic:               105  out of   5720     1%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:    155
   Number with an unused Flip Flop:      51  out of    155    32%  
   Number with an unused LUT:            50  out of    155    32%  
   Number of fully used LUT-FF pairs:    54  out of    155    34%  
   Number of unique control sets:         1

IO Utilization: 
 Number of IOs:                          82
 Number of bonded IOBs:                  82  out of    102    80%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk_pixel                          | BUFGP                  | 104   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: 1.579ns (Maximum Frequency: 633.372MHz)
   Minimum input arrival time before clock: 4.324ns
   Maximum output required time after clock: 3.597ns
   Maximum combinational path delay: 1.872ns

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk_pixel'
  Clock period: 1.579ns (frequency: 633.372MHz)
  Total number of paths / destination ports: 96 / 32
-------------------------------------------------------------------------
Delay:               1.579ns (Levels of Logic = 1)
  Source:            dtm23_0 (FF)
  Destination:       dtm223_0 (FF)
  Source Clock:      clk_pixel rising
  Destination Clock: clk_pixel rising

  Data Path: dtm23_0 to dtm223_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.447   0.827  dtm23_0 (dtm23_0)
     LUT6:I2->O            1   0.203   0.000  dd78_dtm13[7]_select_46_OUT<0>1 (dd78_dtm13[7]_select_46_OUT<0>)
     FDR:D                     0.102          dtm223_0
    ----------------------------------------
    Total                      1.579ns (0.752ns logic, 0.827ns route)
                                       (47.6% logic, 52.4% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk_pixel'
  Total number of paths / destination ports: 632 / 208
-------------------------------------------------------------------------
Offset:              4.324ns (Levels of Logic = 2)
  Source:            rst_n (PAD)
  Destination:       dtm223_0 (FF)
  Destination Clock: clk_pixel rising

  Data Path: rst_n to dtm223_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   1.222   0.579  rst_n_IBUF (rst_n_IBUF)
     INV:I->O            104   0.206   1.887  rst_n_inv1_INV_0 (rst_n_inv)
     FDR:R                     0.430          dtm223_0
    ----------------------------------------
    Total                      4.324ns (1.858ns logic, 2.466ns route)
                                       (43.0% logic, 57.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk_pixel'
  Total number of paths / destination ports: 200 / 200
-------------------------------------------------------------------------
Offset:              3.597ns (Levels of Logic = 1)
  Source:            dout_7 (FF)
  Destination:       dout<7> (PAD)
  Source Clock:      clk_pixel rising

  Data Path: dout_7 to dout<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDR:C->Q              1   0.447   0.579  dout_7 (dout_7)
     OBUF:I->O                 2.571          dout_7_OBUF (dout<7>)
    ----------------------------------------
    Total                      3.597ns (3.018ns logic, 0.579ns route)
                                       (83.9% logic, 16.1% route)

=========================================================================
Timing constraint: Default path analysis
  Total number of paths / destination ports: 144 / 144
-------------------------------------------------------------------------
Delay:               1.872ns (Levels of Logic = 1)
  Source:            din8<7> (PAD)
  Destination:       inst_19_uutcompare8/inst_compare8:a<7> (PAD)

  Data Path: din8<7> to inst_19_uutcompare8/inst_compare8:a<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             3   1.222   0.650  din8_7_IBUF (din8_7_IBUF)
    compare8:a<7>              0.000          inst_19_uutcompare8/inst_compare8
    ----------------------------------------
    Total                      1.872ns (1.222ns logic, 0.650ns route)
                                       (65.3% logic, 34.7% route)

=========================================================================

Cross Clock Domains Report:
--------------------------

Clock to Setup on destination clock clk_pixel
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk_pixel      |    1.579|         |         |         |
---------------+---------+---------+---------+---------+

=========================================================================


Total REAL time to Xst completion: 8.00 secs
Total CPU time to Xst completion: 7.68 secs
 
--> 

Total memory usage is 243940 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    0 (   0 filtered)

