xst -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -ifn "E:/ISE/zhongzhilvbo/zhongzhilvbo.xst" -ofn "E:/ISE/zhongzhilvbo/zhongzhilvbo.syr"
xst -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -ifn "E:/ISE/zhongzhilvbo/zhongzhilvbo.xst" -ofn "E:/ISE/zhongzhilvbo/zhongzhilvbo.syr"
ngdbuild -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -dd _ngo  -nt timestamp -i -p xc3s500e-fg320-4 "zhongzhilvbo.ngc" zhongzhilvbo.ngd
map -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -p xc3s500e-fg320-4 -cm area -pr off -k 4 -c 100 -o zhongzhilvbo_map.ncd zhongzhilvbo.ngd zhongzhilvbo.pcf
par -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -w -intstyle ise -ol std -t 1 zhongzhilvbo_map.ncd zhongzhilvbo.ncd zhongzhilvbo.pcf
trce -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -v 3 -s 4 -xml zhongzhilvbo zhongzhilvbo.ncd -o zhongzhilvbo.twr zhongzhilvbo.pcf
xst -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -ifn "E:/ISE/zhongzhilvbo/zhongzhilvbo.xst" -ofn "E:/ISE/zhongzhilvbo/zhongzhilvbo.syr"
ngdbuild -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -dd _ngo  -nt timestamp -i -p xc3s500e-fg320-4 "zhongzhilvbo.ngc" zhongzhilvbo.ngd
map -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -p xc3s500e-fg320-4 -cm area -pr off -k 4 -c 100 -o zhongzhilvbo_map.ncd zhongzhilvbo.ngd zhongzhilvbo.pcf
par -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -w -intstyle ise -ol std -t 1 zhongzhilvbo_map.ncd zhongzhilvbo.ncd zhongzhilvbo.pcf
trce -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -v 3 -s 4 -xml zhongzhilvbo zhongzhilvbo.ncd -o zhongzhilvbo.twr zhongzhilvbo.pcf -ucf MYUCF.ucf
netgen -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -s 4  -pcf zhongzhilvbo.pcf -sdf_anno true -sdf_path "netgen/par" -insert_glbl true -insert_pp_buffers false -w -dir netgen/par -ofmt verilog -sim zhongzhilvbo.ncd zhongzhilvbo_timesim.v
netgen -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -s 4  -pcf zhongzhilvbo.pcf -sdf_anno true -sdf_path "netgen/map" -insert_glbl true -w -dir netgen/map -ofmt verilog -sim zhongzhilvbo_map.ncd zhongzhilvbo_map.v
xst -ise "E:/ISE/zhongzhilvbo/zhongzhilvbo.ise" -intstyle ise -ifn "E:/ISE/zhongzhilvbo/zhongzhilvbo.xst" -ofn "E:/ISE/zhongzhilvbo/zhongzhilvbo.syr"
xst -intstyle ise -ifn "F:/4_LWHF/8_PX/LAB_NewL2/lab5_1/zhongzhilvbo/zhongzhilvbo.xst" -ofn "F:/4_LWHF/8_PX/LAB_NewL2/lab5_1/zhongzhilvbo/zhongzhilvbo.syr" 
xst -intstyle ise -ifn "F:/4_LWHF/8_PX/LAB_NewL2/lab5_1/zhongzhilvbo/zhongzhilvbo.xst" -ofn "F:/4_LWHF/8_PX/LAB_NewL2/lab5_1/zhongzhilvbo/zhongzhilvbo.syr" 
xst -intstyle ise -ifn "G:/Work/FPGA_CD/chapter4/exp4_7/Midian_fpga/zhongzhilvbo/zhongzhilvbo.xst" -ofn "G:/Work/FPGA_CD/chapter4/exp4_7/Midian_fpga/zhongzhilvbo/zhongzhilvbo.syr" 
