Release 13.2 par O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

WIN-ESOL0RD73FF::  Mon Dec 12 15:23:52 2011

par -w -intstyle ise -ol high -mt off counter_map.ncd counter.ncd counter.pcf 


Constraints file: counter.pcf.
Loading device for application Rf_Device from file '6slx9.nph' in environment G:\Software\ISE_DS\ISE\.
   "counter" is an NCD, version 3.2, device xc6slx9, package tqg144, speed -2

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)


Device speed data version:  "PRODUCTION 1.19 2011-06-20".



Device Utilization Summary:

Slice Logic Utilization:
  Number of Slice Registers:                   258 out of  11,440    2%
    Number used as Flip Flops:                 257
    Number used as Latches:                      1
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        235 out of   5,720    4%
    Number used as logic:                      145 out of   5,720    2%
      Number using O6 output only:              78
      Number using O5 output only:              50
      Number using O5 and O6:                   17
      Number used as ROM:                        0
    Number used as Memory:                      61 out of   1,440    4%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:            61
        Number using O6 output only:            59
        Number using O5 output only:             1
        Number using O5 and O6:                  1
    Number used exclusively as route-thrus:     29
      Number with same-slice register load:     23
      Number with same-slice carry load:         6
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   130 out of   1,430    9%
  Number of LUT Flip Flop pairs used:          316
    Number with an unused Flip Flop:            84 out of     316   26%
    Number with an unused LUT:                  81 out of     316   25%
    Number of fully used LUT-FF pairs:         151 out of     316   47%
    Number of slice register sites lost
      to control set restrictions:               0 out of  11,440    0%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         9 out of     102    8%
    Number of LOCed IOBs:                        1 out of       9   11%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         2 out of      32    6%
  Number of RAMB8BWERs:                          1 out of      64    1%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%


Overall effort level (-ol):   High 
Router effort level (-rl):    High 

Starting initial Timing Analysis.  REAL time: 4 secs 
Finished initial Timing Analysis.  REAL time: 4 secs 

Starting Router


Phase  1  : 1632 unrouted;      REAL time: 5 secs 

Phase  2  : 1057 unrouted;      REAL time: 5 secs 

Phase  3  : 193 unrouted;      REAL time: 6 secs 

Phase  4  : 193 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 7 secs 

Updating file: counter.ncd with current fully routed design.

Phase  5  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 8 secs 

Phase  6  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 8 secs 

Phase  7  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 8 secs 

Phase  8  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 8 secs 

Phase  9  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 8 secs 

Phase 10  : 0 unrouted; (Setup:0, Hold:0, Component Switching Limit:0)     REAL time: 8 secs 
Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 7 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP | BUFGMUX_X2Y11| No   |   73 |  0.111     |  1.502      |
+---------------------+--------------+------+------+------------+-------------+
|    icon_control0<0> |  BUFGMUX_X2Y3| No   |   55 |  0.101     |  1.492      |
+---------------------+--------------+------+------+------------+-------------+
|   icon_control0<13> |         Local|      |    4 |  0.000     |  0.742      |
+---------------------+--------------+------+------+------------+-------------+
|U_icon_pro/U0/iUPDAT |              |      |      |            |             |
|               E_OUT |         Local|      |    1 |  0.000     |  1.039      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.

* The fanout is the number of component pins not the individual BEL loads,
for example SLICE loads not FF loads.

Timing Score: 0 (Setup: 0, Hold: 0, Component Switching Limit: 0)

Number of Timing Constraints that were not applied: 2

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

----------------------------------------------------------------------------------------------------------
  Constraint                                |    Check    | Worst Case |  Best Case | Timing |   Timing   
                                            |             |    Slack   | Achievable | Errors |    Score   
----------------------------------------------------------------------------------------------------------
  TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP       |    11.701ns|     3.299ns|       0|           0
   TO TIMEGRP "J_CLK" 15 ns                 | HOLD        |     1.108ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" | SETUP       |    13.944ns|     1.056ns|       0|           0
   TO TIMEGRP "U_CLK" 15 ns                 | HOLD        |     0.459ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns H | SETUP       |    22.018ns|     7.982ns|       0|           0
  IGH 50%                                   | HOLD        |     0.446ns|            |       0|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_D2_TO_T2_path" TIG               | SETUP       |         N/A|     4.518ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_J2_TO_D2_path" TIG               | N/A         |         N/A|         N/A|     N/A|         N/A
----------------------------------------------------------------------------------------------------------
  PATH "TS_J3_TO_D2_path" TIG               | N/A         |         N/A|         N/A|     N/A|         N/A
----------------------------------------------------------------------------------------------------------
  PATH "TS_J4_TO_D2_path" TIG               | MAXDELAY    |         N/A|     3.885ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_J_TO_D_path" TIG                 | SETUP       |         N/A|     4.754ns|     N/A|           0
----------------------------------------------------------------------------------------------------------
  PATH "TS_D_TO_J_path" TIG                 | SETUP       |         N/A|     4.693ns|     N/A|           0
----------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints List may indicate that the 
   constraint is not analyzed due to the following: No paths covered by this 
   constraint; Other constraints intersect with this constraint; or This 
   constraint was disabled by a Path Tracing Control. Please run the Timespec 
   Interaction Report (TSI) via command line (trce tsi) or Timing Analyzer GUI.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 8 secs 
Total CPU time to PAR completion: 8 secs 

Peak Memory Usage:  293 MB

Placer: Placement generated during map.
Routing: Completed - No errors found.
Timing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 0

Writing design to file counter.ncd



PAR done!
