Release 13.2 Map O.61xd (nt64)
Xilinx Map Application Log File for Design 'counter'

Design Information
------------------
Command Line   : map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol
high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
-pr off -lc off -power off -o counter_map.ncd counter.ngd counter.pcf 
Target Device  : xc6slx9
Target Package : tqg144
Target Speed   : -2
Mapper Version : spartan6 -- $Revision: 1.55 $
Mapped Date    : Mon Dec 12 15:23:35 2011

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Updating timing models...
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 9 secs 
Total CPU  time at the beginning of Placer: 6 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:414db2c9) REAL time: 10 secs 

Phase 2.7  Design Feasibility Check
INFO:Place:834 - Only a subset of IOs are locked. Out of 9 IOs, 1 are locked and
   8 are not locked. If you would like to print the names of these IOs, please
   set the environment variable XIL_PAR_DESIGN_CHECK_VERBOSE to 1. 
Phase 2.7  Design Feasibility Check (Checksum:414db2c9) REAL time: 10 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:cfa13b51) REAL time: 10 secs 

Phase 4.2  Initial Placement for Architecture Specific Features

Phase 4.2  Initial Placement for Architecture Specific Features
(Checksum:dbe33fd1) REAL time: 13 secs 

Phase 5.36  Local Placement Optimization
Phase 5.36  Local Placement Optimization (Checksum:dbe33fd1) REAL time: 13 secs 

Phase 6.30  Global Clock Region Assignment
Phase 6.30  Global Clock Region Assignment (Checksum:dbe33fd1) REAL time: 13 secs 

Phase 7.3  Local Placement Optimization

Phase 7.3  Local Placement Optimization (Checksum:9647227e) REAL time: 13 secs 

Phase 8.5  Local Placement Optimization
Phase 8.5  Local Placement Optimization (Checksum:9647227e) REAL time: 13 secs 

Phase 9.8  Global Placement
..........................
..................
Phase 9.8  Global Placement (Checksum:1341f6a3) REAL time: 14 secs 

Phase 10.5  Local Placement Optimization
Phase 10.5  Local Placement Optimization (Checksum:1341f6a3) REAL time: 14 secs 

Phase 11.18  Placement Optimization
Phase 11.18  Placement Optimization (Checksum:480f49fb) REAL time: 14 secs 

Phase 12.5  Local Placement Optimization
Phase 12.5  Local Placement Optimization (Checksum:480f49fb) REAL time: 14 secs 

Phase 13.34  Placement Validation
Phase 13.34  Placement Validation (Checksum:44bebcf8) REAL time: 14 secs 

Total REAL time to Placer completion: 14 secs 
Total CPU  time to Placer completion: 11 secs 
Running post-placement packing...
Writing output files...
WARNING:PhysDesignRules:372 - Gated clock. Clock net icon_control0<13> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    2
Slice Logic Utilization:
  Number of Slice Registers:                   258 out of  11,440    2%
    Number used as Flip Flops:                 257
    Number used as Latches:                      1
    Number used as Latch-thrus:                  0
    Number used as AND/OR logics:                0
  Number of Slice LUTs:                        235 out of   5,720    4%
    Number used as logic:                      145 out of   5,720    2%
      Number using O6 output only:              78
      Number using O5 output only:              50
      Number using O5 and O6:                   17
      Number used as ROM:                        0
    Number used as Memory:                      61 out of   1,440    4%
      Number used as Dual Port RAM:              0
      Number used as Single Port RAM:            0
      Number used as Shift Register:            61
        Number using O6 output only:            59
        Number using O5 output only:             1
        Number using O5 and O6:                  1
    Number used exclusively as route-thrus:     29
      Number with same-slice register load:     23
      Number with same-slice carry load:         6
      Number with other load:                    0

Slice Logic Distribution:
  Number of occupied Slices:                   130 out of   1,430    9%
  Number of LUT Flip Flop pairs used:          316
    Number with an unused Flip Flop:            84 out of     316   26%
    Number with an unused LUT:                  81 out of     316   25%
    Number of fully used LUT-FF pairs:         151 out of     316   47%
    Number of unique control sets:              53
    Number of slice register sites lost
      to control set restrictions:             272 out of  11,440    2%

  A LUT Flip Flop pair for this architecture represents one LUT paired with
  one Flip Flop within a slice.  A control set is a unique combination of
  clock, reset, set, and enable signals for a registered element.
  The Slice Logic Distribution report is not meaningful if the design is
  over-mapped for a non-slice resource or if Placement fails.

IO Utilization:
  Number of bonded IOBs:                         9 out of     102    8%
    Number of LOCed IOBs:                        1 out of       9   11%

Specific Feature Utilization:
  Number of RAMB16BWERs:                         2 out of      32    6%
  Number of RAMB8BWERs:                          1 out of      64    1%
  Number of BUFIO2/BUFIO2_2CLKs:                 0 out of      32    0%
  Number of BUFIO2FB/BUFIO2FB_2CLKs:             0 out of      32    0%
  Number of BUFG/BUFGMUXs:                       2 out of      16   12%
    Number used as BUFGs:                        2
    Number used as BUFGMUX:                      0
  Number of DCM/DCM_CLKGENs:                     0 out of       4    0%
  Number of ILOGIC2/ISERDES2s:                   0 out of     200    0%
  Number of IODELAY2/IODRP2/IODRP2_MCBs:         0 out of     200    0%
  Number of OLOGIC2/OSERDES2s:                   0 out of     200    0%
  Number of BSCANs:                              1 out of       4   25%
  Number of BUFHs:                               0 out of     128    0%
  Number of BUFPLLs:                             0 out of       8    0%
  Number of BUFPLL_MCBs:                         0 out of       4    0%
  Number of DSP48A1s:                            0 out of      16    0%
  Number of ICAPs:                               0 out of       1    0%
  Number of MCBs:                                0 out of       2    0%
  Number of PCILOGICSEs:                         0 out of       2    0%
  Number of PLL_ADVs:                            0 out of       2    0%
  Number of PMVs:                                0 out of       1    0%
  Number of STARTUPs:                            0 out of       1    0%
  Number of SUSPEND_SYNCs:                       0 out of       1    0%

  Number of RPM macros:            9
Average Fanout of Non-Clock Nets:                2.93

Peak Memory Usage:  334 MB
Total REAL time to MAP completion:  15 secs 
Total CPU time to MAP completion:   11 secs 

Mapping completed.
See MAP report file "counter_map.mrp" for details.
