Release 13.2 - xst O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to xst/projnav.tmp


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
 
--> Parameter xsthdpdir set to xst


Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.11 secs
 
--> Reading design: adder_top.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Parsing
  3) HDL Elaboration
  4) HDL Synthesis
       4.1) HDL Synthesis Report
  5) Advanced HDL Synthesis
       5.1) Advanced HDL Synthesis Report
  6) Low Level Synthesis
  7) Partition Report
  8) Design Summary
       8.1) Primitive and Black Box Usage
       8.2) Device utilization summary
       8.3) Partition Resource Summary
       8.4) Timing Report
            8.4.1) Clock Information
            8.4.2) Asynchronous Control Signals Information
            8.4.3) Timing Summary
            8.4.4) Timing Details
            8.4.5) Cross Clock Domains Report


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "adder_top.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "adder_top"
Output Format                      : NGC
Target Device                      : xc6slx9-3-tqg144

---- Source Options
Top Module Name                    : adder_top
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Safe Implementation                : No
FSM Style                          : LUT
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Shift Register Extraction          : YES
ROM Style                          : Auto
Resource Sharing                   : YES
Asynchronous To Synchronous        : NO
Shift Register Minimum Size        : 2
Use DSP Block                      : Auto
Automatic Register Balancing       : No

---- Target Options
LUT Combining                      : Auto
Reduce Control Sets                : Auto
Add IO Buffers                     : YES
Global Maximum Fanout              : 100000
Add Generic Clock Buffer(BUFG)     : 16
Register Duplication               : YES
Optimize Instantiated Primitives   : NO
Use Clock Enable                   : Auto
Use Synchronous Set                : Auto
Use Synchronous Reset              : Auto
Pack IO Registers into IOBs        : Auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Power Reduction                    : NO
Keep Hierarchy                     : No
Netlist Hierarchy                  : As_Optimized
RTL Output                         : Yes
Global Optimization                : AllClockNets
Read Cores                         : YES
Write Timing Constraints           : NO
Cross Clock Analysis               : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : Maintain
Slice Utilization Ratio            : 100
BRAM Utilization Ratio             : 100
DSP48 Utilization Ratio            : 100
Auto BRAM Packing                  : NO
Slice Utilization Ratio Delta      : 5

---- Other Options
Cores Search Directories           : {"ipcore_dir"  }

=========================================================================


=========================================================================
*                          HDL Parsing                                  *
=========================================================================
Analyzing Verilog file \"G:\Work\FPGA_CD\chapter4\exp4_1\ipcore_dir\adder.v\" into library work
Parsing module <adder>.
Analyzing Verilog file \"G:\Work\FPGA_CD\chapter4\exp4_1\adder_top.v\" into library work
Parsing module <adder_top>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating module <adder_top>.

Elaborating module <adder>.
WARNING:HDLCompiler:189 - "G:\Work\FPGA_CD\chapter4\exp4_1\adder_top.v" Line 28: Size mismatch in connection of port <a>. Formal port size is 8-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:189 - "G:\Work\FPGA_CD\chapter4\exp4_1\adder_top.v" Line 29: Size mismatch in connection of port <b>. Formal port size is 8-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:189 - "G:\Work\FPGA_CD\chapter4\exp4_1\adder_top.v" Line 32: Size mismatch in connection of port <s>. Formal port size is 8-bit while actual signal size is 1-bit.
WARNING:HDLCompiler:1127 - "G:\Work\FPGA_CD\chapter4\exp4_1\adder_top.v" Line 32: Assignment to s ignored, since the identifier is never used
WARNING:HDLCompiler:634 - "G:\Work\FPGA_CD\chapter4\exp4_1\adder_top.v" Line 28: Net <a> does not have a driver.
WARNING:HDLCompiler:634 - "G:\Work\FPGA_CD\chapter4\exp4_1\adder_top.v" Line 29: Net <b> does not have a driver.
WARNING:HDLCompiler:634 - "G:\Work\FPGA_CD\chapter4\exp4_1\adder_top.v" Line 31: Net <ce> does not have a driver.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <adder_top>.
    Related source file is "g:/work/fpga_cd/chapter4/exp4_1/adder_top.v".
WARNING:Xst:647 - Input <x1_in<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <x2_in<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "g:/work/fpga_cd/chapter4/exp4_1/adder_top.v" line 27: Output port <s> of the instance <inst_adder> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <a> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <b> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <ce> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <adder_top> synthesized.

=========================================================================
HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <ipcore_dir/adder.ngc>.
Loading core <adder> for timing and area information for instance <inst_adder>.

=========================================================================
Advanced HDL Synthesis Report

Found no macro
=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <adder_top> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block adder_top, actual ratio is 0.

Final Macro Processing ...

=========================================================================
Final Register Report

Found no macro
=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Top Level Output File Name         : adder_top.ngc

Primitive and Black Box Usage:
------------------------------
# BELS                             : 25
#      GND                         : 2
#      LUT2                        : 8
#      MUXCY                       : 7
#      XORCY                       : 8
# FlipFlops/Latches                : 8
#      FDE                         : 8
# Clock Buffers                    : 1
#      BUFGP                       : 1

Device utilization summary:
---------------------------

Selected Device : 6slx9tqg144-3 


Slice Logic Utilization: 
 Number of Slice Registers:               8  out of  11440     0%  
 Number of Slice LUTs:                    8  out of   5720     0%  
    Number used as Logic:                 8  out of   5720     0%  

Slice Logic Distribution: 
 Number of LUT Flip Flop pairs used:     16
   Number with an unused Flip Flop:       8  out of     16    50%  
   Number with an unused LUT:             8  out of     16    50%  
   Number of fully used LUT-FF pairs:     0  out of     16     0%  
   Number of unique control sets:         1

IO Utilization: 
 Number of IOs:                          25
 Number of bonded IOBs:                   1  out of    102     0%  

Specific Feature Utilization:
 Number of BUFG/BUFGCTRLs:                1  out of     16     6%  

---------------------------
Partition Resource Summary:
---------------------------

  No Partitions were found in this design.

---------------------------


=========================================================================
Timing Report

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 8     |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -3

   Minimum period: No path found
   Minimum input arrival time before clock: No path found
   Maximum output required time after clock: No path found
   Maximum combinational path delay: No path found

Timing Details:
---------------
All values displayed in nanoseconds (ns)

=========================================================================

Cross Clock Domains Report:
--------------------------

=========================================================================


Total REAL time to Xst completion: 6.00 secs
Total CPU time to Xst completion: 5.99 secs
 
--> 

Total memory usage is 242916 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :   12 (   0 filtered)
Number of infos    :    1 (   0 filtered)

