Release 13.2 Drc O.61xd (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Mon Dec 12 15:24:13 2011

drc -z counter.ncd counter.pcf

WARNING:PhysDesignRules:372 - Gated clock. Clock net icon_control0<13> is
   sourced by a combinatorial pin. This is not good design practice. Use the CE
   pin to control the loading of data into the flip-flop.
WARNING:PhysDesignRules:2410 - This design is using one or more 9K Block RAMs
   (RAMB8BWER).  9K Block RAM initialization data, both user defined and
   default, may be incorrect and should not be used.  For more information,
   please reference Xilinx Answer Record 39999.
DRC detected 0 errors and 2 warnings.  Please see the previously displayed
individual error or warning messages for more details.
