Model {
  Name			  "FreqSweep"
  Version		  7.0
  MdlSubVersion		  0
  GraphicalInterface {
    NumRootInports	    0
    NumRootOutports	    0
    ParameterArgumentNames  ""
    ComputedModelVersion    "1.314"
    NumModelReferences	    0
    NumTestPointedSignals   0
  }
  SavedCharacterEncoding  "ibm-5348_P100-1997"
  PreLoadFcn		  "close all
\nclear all
\nFilterOrder = 32
\nInputBitWidth = 8
\nLowPassFreqBand = [0 0.01 0.2 1];
\nLowPassMagnBand = [1 0.9 0.0001 0.0001];
\n
\nFlCoef = firls(FilterOrder,LowPassFreqBand,LowPassMagnBand);
\n
\nCoefBitWidth = InputBitWidth + ceil(log2((max(abs(FlCoef))/min(abs(FlCoef)))))
\n
\nScalingFactor = (2^(CoefBitWidth-1))-1;
\nFpCoef = fix(ScalingFactor * FlCoef);
\n%plot(FpCoef,'o');
\n%title('Fixed-point scaled coefficient value');
\nImpulseData = zeros(1,1000);
\nImpulseData(1) = 100;
\nh = conv(ImpulseData,FpCoef);
\n%fftplot(h);
\n%title('FIR Frequency response');
\nFirSamplingPeriod=1;
\n
\ncordic_precision=20;
\nScalingFactor = (2^(cordic_precision-1))-1;
\nK=1.0;
\nfor i=1:cordic_precision
\n  cordic_atan_table(i) = round(atan(K)*ScalingFactor);
\n  K=0.5*K;
\nend;
\n%disp(['cordic_precision =' num2str(cordic_precision)]);
\n%disp(['cordic_atan_table =' num2str(cordic_atan_table)]);
\n"
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  InitFcn		  "%% DSPBuilder Start\nalt_dspbuilder_update_model(bdroot)\n%% DSPBuilder End\n"
  Created		  "Tue Jan 06 15:21:40 2004"
  Creator		  "tian yun"
  UpdateHistory		  "UpdateHistoryNever"
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  LastModifiedBy	  "tian yun"
  ModifiedDateFormat	  "%<Auto>"
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	  WriteAfterReadMsg	  "UseLocalSettings"
	  AlgebraicLoopMsg	  "warning"
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	  CheckSSInitialOutputMsg on
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	  InvalidFcnCallConnMsg	  "error"
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    Block {
      BlockType		      Product
      Name		      "Product"
      Ports		      [2, 1]
      Position		      [170, 126, 215, 159]
      InputSameDT	      off
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
      RndMeth		      "Floor"
    }
    Block {
      BlockType		      Reference
      Name		      "Ramp"
      Ports		      [0, 1]
      Position		      [20, 130, 50, 160]
      SourceBlock	      "simulink/Sources/Ramp"
      SourceType	      "Ramp"
      ShowPortLabels	      "FromPortIcon"
      SystemSampleTime	      "-1"
      FunctionWithSeparateData off
      RTWMemSecFuncInitTerm   "Inherit from model"
      RTWMemSecFuncExecute    "Inherit from model"
      RTWMemSecDataConstants  "Inherit from model"
      RTWMemSecDataInternal   "Inherit from model"
      RTWMemSecDataParameters "Inherit from model"
      slope		      ".01"
      start		      "0"
      X0		      "0"
      VectorParams1D	      on
    }
    Block {
      BlockType		      Reference
      Name		      "Round"
      Ports		      [1, 1]
      Position		      [405, 135, 470, 155]
      ForegroundColor	      "blue"
      SourceBlock	      "allblocks_alteradspbuilder2/Round"
      SourceType	      "Round AlteraBlockset"
      BusType		      "Signed Integer"
      bwl		      "21"
      bwr		      "0"
      bitsToRemove	      "1"
      roundMode		      "ROUND_UP_SYM"
      userRoundMode	      "Round Away From Zero"
      pipeline		      on
      pipeline_display	      "1"
      use_ena		      off
      use_aclr		      off
    }
    Block {
      BlockType		      Scope
      Name		      "SW_Scope"
      Ports		      [2]
      Position		      [880, 130, 910, 185]
      Floating		      off
      Location		      [11, 60, 1163, 529]
      Open		      off
      NumInputPorts	      "2"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
      }
      YMin		      "-1.1e+006~-550000"
      YMax		      "1.1e+006~550000"
      SaveName		      "ScopeData1"
      DataFormat	      "StructureWithTime"
      Decimation	      "20"
      SampleTime	      "0"
    }
    Block {
      BlockType		      SignalSpecification
      Name		      "Signal Specification"
      Position		      [85, 135, 130, 155]
      SampleTime	      "1"
      OutDataType	      "sfix(16)"
      OutScaling	      "2^0"
    }
    Block {
      BlockType		      Reference
      Name		      "SignalCompiler"
      Ports		      []
      Position		      [15, 15, 84, 62]
      SourceBlock	      "allblocks_alteradspbuilder2/Signal Compiler"
      SourceType	      "Signal Compiler AlteraBlockset"
      DeviceFamily	      "Stratix II"
      DeviceName	      "AUTO"
      EnableSignalTap	      off
      SignalTapDepth	      "128"
      UseBoardBlock	      off
      StpUseDefaultClock      on
      StpClock		      "Clock"
      ExportDir		      "."
    }
    Line {
      SrcBlock		      "Ramp"
      SrcPort		      1
      DstBlock		      "Signal Specification"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Product"
      SrcPort		      1
      DstBlock		      "Input"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Signal Specification"
      SrcPort		      1
      Points		      [0, 0; 10, 0]
      Branch {
	Points			[0, -10]
	DstBlock		"Product"
	DstPort			1
      }
      Branch {
	Points			[0, 5]
	DstBlock		"Product"
	DstPort			2
      }
    }
    Line {
      Name		      "Filtered Sine"
      Labels		      [0, 0]
      SrcBlock		      "OutputFilter"
      SrcPort		      1
      DstBlock		      "SW_Scope"
      DstPort		      1
    }
    Line {
      SrcBlock		      "Input"
      SrcPort		      1
      DstBlock		      "Round"
      DstPort		      1
    }
    Line {
      Labels		      [0, 0]
      SrcBlock		      "Round"
      SrcPort		      1
      DstBlock		      "OutputFilter"
      DstPort		      1
    }
    Annotation {
      Name		      "(c) 2007 Altera Corporation. All rights reserved.  Altera products are protected under numerous U.S. and foreign patents, maskwork rights, copyrights and other intellectual property laws. \nThis reference design file, and your use hereof, is subject to and governed by the terms and conditions of the applicable Altera Reference Design License Agreement (found at www.altera.com).\nBy using this reference design file, you indicate your acceptance of such terms and conditions between you and Altera Corporation. \nIn the event that you do not agree with such terms and conditions, you may not use the reference design file and please promptly destroy any copies you have made.\nThis reference design file being provided on an \"as-is\" basis and as an accommodation and therefore all warranties, representations or guarantees of any kind (whether express, implied or statutory)\nincluding, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed.\nBy making this reference design file available, Altera expressly does not recommend, suggest or require that this reference design file be used in combination with any other product not provided by Altera"
      Position		      [6, 326]
      HorizontalAlignment     "left"
      ForegroundColor	      "blue"
    }
  }
}
