adder_top Project Status (05/06/2012 - 18:19:17)
Project File: | exp4_1.xise | Parser Errors: | No Errors
Module Name: | adder_top | Implementation State: | Synthesized
Target Device: | xc6slx9-3tqg144 | Errors: | No Errors
Product Version: | ISE 13.2 | Warnings: | 12 Warnings (0 new)
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slice Registers | 8 | 11440 | 0%
Number of Slice LUTs | 8 | 5720 | 0%
Number of fully used LUT-FF pairs | 0 | 16 | 0%
Number of bonded IOBs | 1 | 102 | 0%
Number of BUFG/BUFGCTRLs | 1 | 16 | 6%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | ΦάΘΥ ΞεΤΒ 6 18:19:16 2012 | 0 | 12 Warnings (0 new) | 1 Info (1 new)
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 05/06/2012 - 18:19:17