--------------------------------------------------------------------------------
Release 13.2 Trace  (nt64)
Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

G:\Software\ISE_DS\ISE\bin\nt64\unwrapped\trce.exe -intstyle ise -v 3 -s 2 -n 3
-fastpaths -xml counter.twx counter.ncd -o counter.twr counter.pcf -ucf ucf.ucf

Design file:              counter.ncd
Physical constraint file: counter.pcf
Device,package,speed:     xc6slx9,tqg144,C,-2 (PRODUCTION 1.19 2011-06-20)
Report level:             verbose report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.

================================================================================
Timing constraint: PATH "TS_D2_TO_T2_path" TIG;

 3 paths analyzed, 3 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO (SLICE_X12Y35.A1), 1 path
--------------------------------------------------------------------------------
Delay (setup path):     4.518ns (data path - clock path skew + uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO (FF)
  Data Path Delay:      4.483ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<13> falling
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y33.AQ      Tcklo                 0.515   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    SLICE_X12Y33.B1      net (fanout=1)        0.773   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
    SLICE_X12Y33.B       Tilo                  0.254   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/Mmux_DIRTY_dstat11
    SLICE_X12Y33.D1      net (fanout=2)        0.604   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat
    SLICE_X12Y33.CMUX    Topdc                 0.456   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O121_F
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O121
    SLICE_X12Y35.C4      net (fanout=1)        0.721   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O120
    SLICE_X12Y35.C       Tilo                  0.255   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O124
    SLICE_X12Y35.A1      net (fanout=1)        0.566   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O123
    SLICE_X12Y35.CLK     Tas                   0.339   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O125
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    -------------------------------------------------  ---------------------------
    Total                                      4.483ns (1.819ns logic, 2.664ns route)
                                                       (40.6% logic, 59.4% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE (SLICE_X13Y32.AX), 1 path
--------------------------------------------------------------------------------
Delay (setup path):     2.402ns (data path - clock path skew + uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE (FF)
  Data Path Delay:      2.367ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<13> falling
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y33.AQ      Tcklo                 0.515   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    SLICE_X12Y33.B1      net (fanout=1)        0.773   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
    SLICE_X12Y33.B       Tilo                  0.254   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/Mmux_DIRTY_dstat11
    SLICE_X13Y32.AX      net (fanout=2)        0.711   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat
    SLICE_X13Y32.CLK     Tdick                 0.114   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE
    -------------------------------------------------  ---------------------------
    Total                                      2.367ns (0.883ns logic, 1.484ns route)
                                                       (37.3% logic, 62.7% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE (SLICE_X12Y33.B1), 1 path
--------------------------------------------------------------------------------
Delay (setup path):     1.662ns (data path - clock path skew + uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE (FF)
  Data Path Delay:      1.627ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<13> falling
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y33.AQ      Tcklo                 0.515   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    SLICE_X12Y33.B1      net (fanout=1)        0.773   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
    SLICE_X12Y33.CLK     Tas                   0.339   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/Mmux_DIRTY_dstat11
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE
    -------------------------------------------------  ---------------------------
    Total                                      1.627ns (0.854ns logic, 0.773ns route)
                                                       (52.5% logic, 47.5% route)

--------------------------------------------------------------------------------

Hold Paths: PATH "TS_D2_TO_T2_path" TIG;
--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE (SLICE_X12Y33.B1), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      0.781ns (datapath - clock path skew - uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE (FF)
  Data Path Delay:      0.816ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<13> falling
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y33.AQ      Tcklo                 0.235   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    SLICE_X12Y33.B1      net (fanout=1)        0.384   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
    SLICE_X12Y33.CLK     Tah         (-Th)    -0.197   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/Mmux_DIRTY_dstat11
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDPE
    -------------------------------------------------  ---------------------------
    Total                                      0.816ns (0.432ns logic, 0.384ns route)
                                                       (52.9% logic, 47.1% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE (SLICE_X13Y32.AX), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      1.163ns (datapath - clock path skew - uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE (FF)
  Data Path Delay:      1.198ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<13> falling
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y33.AQ      Tcklo                 0.235   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    SLICE_X12Y33.B1      net (fanout=1)        0.384   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
    SLICE_X12Y33.B       Tilo                  0.156   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/Mmux_DIRTY_dstat11
    SLICE_X13Y32.AX      net (fanout=2)        0.364   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat
    SLICE_X13Y32.CLK     Tckdi       (-Th)    -0.059   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D0
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_FDCE
    -------------------------------------------------  ---------------------------
    Total                                      1.198ns (0.450ns logic, 0.748ns route)
                                                       (37.6% logic, 62.4% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO (SLICE_X12Y35.A1), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      2.208ns (datapath - clock path skew - uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO (FF)
  Data Path Delay:      2.243ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<13> falling
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y33.AQ      Tcklo                 0.235   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    SLICE_X12Y33.B1      net (fanout=1)        0.384   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
    SLICE_X12Y33.B       Tilo                  0.156   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/Mmux_DIRTY_dstat11
    SLICE_X12Y33.D1      net (fanout=2)        0.274   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_dstat
    SLICE_X12Y33.CMUX    Topdc                 0.245   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_D1
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O121_F
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O121
    SLICE_X12Y35.C4      net (fanout=1)        0.337   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O120
    SLICE_X12Y35.C       Tilo                  0.156   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O124
    SLICE_X12Y35.A1      net (fanout=1)        0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O123
    SLICE_X12Y35.CLK     Tah         (-Th)    -0.197   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O125
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    -------------------------------------------------  ---------------------------
    Total                                      2.243ns (0.989ns logic, 1.254ns route)
                                                       (44.1% logic, 55.9% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: PATH "TS_J2_TO_D2_path" TIG;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: PATH "TS_J3_TO_D2_path" TIG;

 0 paths analyzed, 0 endpoints analyzed, 0 failing endpoints
 0 timing errors detected.
--------------------------------------------------------------------------------

================================================================================
Timing constraint: PATH "TS_J4_TO_D2_path" TIG;

 12 paths analyzed, 2 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (SLICE_X15Y33.CLK), 11 paths
--------------------------------------------------------------------------------
Delay (setup path):     3.885ns (data path)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Data Path Delay:      3.885ns (Levels of Logic = 2)
  Source Clock:         icon_control0<0> rising at 0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y46.DQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET
    SLICE_X15Y39.C5      net (fanout=8)        1.362   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
    SLICE_X15Y39.C       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT
    SLICE_X14Y37.D2      net (fanout=1)        0.762   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<9>
    SLICE_X14Y37.D       Tilo                  0.235   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE
    SLICE_X15Y33.CLK     net (fanout=4)        0.742   icon_control0<13>
    -------------------------------------------------  ---------------------------
    Total                                      3.885ns (1.019ns logic, 2.866ns route)
                                                       (26.2% logic, 73.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.819ns (data path)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Data Path Delay:      3.819ns (Levels of Logic = 2)
  Source Clock:         icon_control0<0> rising at 0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y46.CQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[10].I_NE0.U_TARGET
    SLICE_X15Y39.C3      net (fanout=8)        1.296   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<10>
    SLICE_X15Y39.C       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[9].U_LUT
    SLICE_X14Y37.D2      net (fanout=1)        0.762   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<9>
    SLICE_X14Y37.D       Tilo                  0.235   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE
    SLICE_X15Y33.CLK     net (fanout=4)        0.742   icon_control0<13>
    -------------------------------------------------  ---------------------------
    Total                                      3.819ns (1.019ns logic, 2.800ns route)
                                                       (26.7% logic, 73.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     3.815ns (data path)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Data Path Delay:      3.815ns (Levels of Logic = 2)
  Source Clock:         icon_control0<0> rising at 0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y46.BMUX    Tshcko                0.576   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[7].I_NE0.U_TARGET
    SLICE_X12Y45.C3      net (fanout=4)        0.598   U_icon_pro/U0/U_ICON/iCOMMAND_GRP<1>
    SLICE_X12Y45.C       Tilo                  0.255   icon_control0<4>
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/U_CMDGRP0
    SLICE_X14Y37.D1      net (fanout=9)        1.409   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iCOMMAND_GRP_SEL<0>
    SLICE_X14Y37.D       Tilo                  0.235   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_HALT_XFER/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[9].U_LCE
    SLICE_X15Y33.CLK     net (fanout=4)        0.742   icon_control0<13>
    -------------------------------------------------  ---------------------------
    Total                                      3.815ns (1.066ns logic, 2.749ns route)
                                                       (27.9% logic, 72.1% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (SLICE_X15Y33.SR), 1 path
--------------------------------------------------------------------------------
Delay (setup path):     2.387ns (data path - clock path skew + uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Data Path Delay:      1.751ns (Levels of Logic = 0)
  Clock Path Skew:      -0.601ns (2.923 - 3.524)
  Source Clock:         clk_BUFGP rising
  Destination Clock:    icon_control0<13> falling
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y38.AQ      Tcko                  0.430   U_ila_pro_0/U0/I_NO_D.U_ILA/iARM
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD
    SLICE_X15Y33.SR      net (fanout=10)       1.041   U_ila_pro_0/U0/I_NO_D.U_ILA/iARM
    SLICE_X15Y33.CLK     Trck                  0.280   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    -------------------------------------------------  ---------------------------
    Total                                      1.751ns (0.710ns logic, 1.041ns route)
                                                       (40.5% logic, 59.5% route)

--------------------------------------------------------------------------------

Hold Paths: PATH "TS_J4_TO_D2_path" TIG;
--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (SLICE_X15Y33.SR), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      -0.066ns (datapath - clock path skew - uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC (LATCH)
  Data Path Delay:      0.888ns (Levels of Logic = 0)
  Clock Path Skew:      0.954ns (2.042 - 1.088)
  Source Clock:         clk_BUFGP rising
  Destination Clock:    icon_control0<13> falling
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X17Y38.AQ      Tcko                  0.198   U_ila_pro_0/U0/I_NO_D.U_ILA/iARM
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_GEN_DELAY[3].U_FD
    SLICE_X15Y33.SR      net (fanout=10)       0.535   U_ila_pro_0/U0/I_NO_D.U_ILA/iARM
    SLICE_X15Y33.CLK     Tremck      (-Th)    -0.155   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DIRTY_SEL
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DIRTY_LDC
    -------------------------------------------------  ---------------------------
    Total                                      0.888ns (0.353ns logic, 0.535ns route)
                                                       (39.8% logic, 60.2% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 
15 ns;

 18 paths analyzed, 18 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   3.299ns.
--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (SLICE_X12Y47.CE), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    11.701ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
  Requirement:          15.000ns
  Data Path Delay:      3.264ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y59.AQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    SLICE_X12Y46.A4      net (fanout=3)        1.634   U_icon_pro/U0/U_ICON/iDATA_CMD
    SLICE_X12Y46.A       Tilo                  0.254   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_TARGET_CE
    SLICE_X12Y47.CE      net (fanout=2)        0.538   U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
    SLICE_X12Y47.CLK     Tceck                 0.313   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
    -------------------------------------------------  ---------------------------
    Total                                      3.264ns (1.092ns logic, 2.172ns route)
                                                       (33.5% logic, 66.5% route)

--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (SLICE_X12Y47.CE), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    11.745ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (FF)
  Requirement:          15.000ns
  Data Path Delay:      3.220ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y59.AQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    SLICE_X12Y46.A4      net (fanout=3)        1.634   U_icon_pro/U0/U_ICON/iDATA_CMD
    SLICE_X12Y46.A       Tilo                  0.254   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_TARGET_CE
    SLICE_X12Y47.CE      net (fanout=2)        0.538   U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
    SLICE_X12Y47.CLK     Tceck                 0.269   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET
    -------------------------------------------------  ---------------------------
    Total                                      3.220ns (1.048ns logic, 2.172ns route)
                                                       (32.5% logic, 67.5% route)

--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET (SLICE_X12Y47.CE), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    11.748ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET (FF)
  Requirement:          15.000ns
  Data Path Delay:      3.217ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y59.AQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    SLICE_X12Y46.A4      net (fanout=3)        1.634   U_icon_pro/U0/U_ICON/iDATA_CMD
    SLICE_X12Y46.A       Tilo                  0.254   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_TARGET_CE
    SLICE_X12Y47.CE      net (fanout=2)        0.538   U_icon_pro/U0/U_ICON/U_CMD/iTARGET_CE
    SLICE_X12Y47.CLK     Tceck                 0.266   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[15].I_EQ0.U_TARGET
    -------------------------------------------------  ---------------------------
    Total                                      3.217ns (1.045ns logic, 2.172ns route)
                                                       (32.5% logic, 67.5% route)

--------------------------------------------------------------------------------
Hold Paths: TS_U_TO_J = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "J_CLK" 15 ns;
--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (SLICE_X15Y48.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.108ns (requirement - (clock path skew + uncertainty - data path))
  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.143ns (Levels of Logic = 1)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Fast Process Corner: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y59.AQ      Tcko                  0.234   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    SLICE_X14Y49.A6      net (fanout=3)        0.643   U_icon_pro/U0/U_ICON/iDATA_CMD
    SLICE_X14Y49.A       Tilo                  0.142   U_icon_pro/U0/U_ICON/U_SYNC/iDATA_CMD_n
                                                       U_icon_pro/U0/U_ICON/U_SYNC/U_iDATA_CMD_n
    SLICE_X15Y48.SR      net (fanout=2)        0.255   U_icon_pro/U0/U_ICON/U_SYNC/iDATA_CMD_n
    SLICE_X15Y48.CLK     Tcksr       (-Th)     0.131   U_icon_pro/U0/U_ICON/iSYNC
                                                       U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
    -------------------------------------------------  ---------------------------
    Total                                      1.143ns (0.245ns logic, 0.898ns route)
                                                       (21.4% logic, 78.6% route)
--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR (SLICE_X15Y49.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.206ns (requirement - (clock path skew + uncertainty - data path))
  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.241ns (Levels of Logic = 1)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Fast Process Corner: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y59.AQ      Tcko                  0.234   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    SLICE_X14Y49.A6      net (fanout=3)        0.643   U_icon_pro/U0/U_ICON/iDATA_CMD
    SLICE_X14Y49.A       Tilo                  0.142   U_icon_pro/U0/U_ICON/U_SYNC/iDATA_CMD_n
                                                       U_icon_pro/U0/U_ICON/U_SYNC/U_iDATA_CMD_n
    SLICE_X15Y49.SR      net (fanout=2)        0.361   U_icon_pro/U0/U_ICON/U_SYNC/iDATA_CMD_n
    SLICE_X15Y49.CLK     Tcksr       (-Th)     0.139   U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<3>
                                                       U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[5].I_NE0.U_FDR
    -------------------------------------------------  ---------------------------
    Total                                      1.241ns (0.237ns logic, 1.004ns route)
                                                       (19.1% logic, 80.9% route)
--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR (SLICE_X15Y49.SR), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      1.207ns (requirement - (clock path skew + uncertainty - data path))
  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR (FF)
  Requirement:          0.000ns
  Data Path Delay:      1.242ns (Levels of Logic = 1)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Fast Process Corner: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y59.AQ      Tcko                  0.234   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    SLICE_X14Y49.A6      net (fanout=3)        0.643   U_icon_pro/U0/U_ICON/iDATA_CMD
    SLICE_X14Y49.A       Tilo                  0.142   U_icon_pro/U0/U_ICON/U_SYNC/iDATA_CMD_n
                                                       U_icon_pro/U0/U_ICON/U_SYNC/U_iDATA_CMD_n
    SLICE_X15Y49.SR      net (fanout=2)        0.361   U_icon_pro/U0/U_ICON/U_SYNC/iDATA_CMD_n
    SLICE_X15Y49.CLK     Tcksr       (-Th)     0.138   U_icon_pro/U0/U_ICON/U_SYNC/iSYNC_WORD<3>
                                                       U_icon_pro/U0/U_ICON/U_SYNC/G_SYNC_WORD[4].I_NE0.U_FDR
    -------------------------------------------------  ---------------------------
    Total                                      1.242ns (0.238ns logic, 1.004ns route)
                                                       (19.2% logic, 80.8% route)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 
15 ns;

 1 path analyzed, 1 endpoint analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
 Maximum delay is   1.056ns.
--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_iDATA_CMD (SLICE_X20Y59.A6), 1 path
--------------------------------------------------------------------------------
Slack (setup paths):    13.944ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Requirement:          15.000ns
  Data Path Delay:      1.021ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
  Destination Clock:    U_icon_pro/U0/iUPDATE_OUT rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_iDATA_CMD
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y59.AQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    SLICE_X20Y59.A6      net (fanout=3)        0.157   U_icon_pro/U0/U_ICON/iDATA_CMD
    SLICE_X20Y59.CLK     Tas                   0.339   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD_n
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    -------------------------------------------------  ---------------------------
    Total                                      1.021ns (0.864ns logic, 0.157ns route)
                                                       (84.6% logic, 15.4% route)

--------------------------------------------------------------------------------
Hold Paths: TS_U_TO_U = MAXDELAY FROM TIMEGRP "U_CLK" TO TIMEGRP "U_CLK" 15 ns;
--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_iDATA_CMD (SLICE_X20Y59.A6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.459ns (requirement - (clock path skew + uncertainty - data path))
  Source:               U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Destination:          U_icon_pro/U0/U_ICON/U_iDATA_CMD (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.459ns (Levels of Logic = 1)
  Positive Clock Path Skew: 0.000ns
  Source Clock:         U_icon_pro/U0/iUPDATE_OUT rising
  Destination Clock:    U_icon_pro/U0/iUPDATE_OUT rising
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: U_icon_pro/U0/U_ICON/U_iDATA_CMD to U_icon_pro/U0/U_ICON/U_iDATA_CMD
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X20Y59.AQ      Tcko                  0.234   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    SLICE_X20Y59.A6      net (fanout=3)        0.028   U_icon_pro/U0/U_ICON/iDATA_CMD
    SLICE_X20Y59.CLK     Tah         (-Th)    -0.197   U_icon_pro/U0/U_ICON/iDATA_CMD
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD_n
                                                       U_icon_pro/U0/U_ICON/U_iDATA_CMD
    -------------------------------------------------  ---------------------------
    Total                                      0.459ns (0.431ns logic, 0.028ns route)
                                                       (93.9% logic, 6.1% route)
--------------------------------------------------------------------------------

================================================================================
Timing constraint: PATH "TS_J_TO_D_path" TIG;

 393 paths analyzed, 109 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE (SLICE_X19Y39.SR), 11 paths
--------------------------------------------------------------------------------
Delay (setup path):     4.754ns (data path - clock path skew + uncertainty)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE (FF)
  Data Path Delay:      4.719ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.AQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
    SLICE_X12Y47.B6      net (fanout=4)        0.796   U_icon_pro/U0/U_ICON/iCORE_ID<0>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X13Y39.B5      net (fanout=10)       0.985   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X13Y39.B       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE
    SLICE_X13Y39.A5      net (fanout=4)        0.244   icon_control0<5>
    SLICE_X13Y39.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR
    SLICE_X19Y39.SR      net (fanout=3)        1.072   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR
    SLICE_X19Y39.CLK     Trck                  0.325   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly<0>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE
    -------------------------------------------------  ---------------------------
    Total                                      4.719ns (1.622ns logic, 3.097ns route)
                                                       (34.4% logic, 65.6% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.703ns (data path - clock path skew + uncertainty)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE (FF)
  Data Path Delay:      4.668ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.CQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET
    SLICE_X12Y47.B2      net (fanout=4)        0.745   U_icon_pro/U0/U_ICON/iCORE_ID<2>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X13Y39.B5      net (fanout=10)       0.985   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X13Y39.B       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE
    SLICE_X13Y39.A5      net (fanout=4)        0.244   icon_control0<5>
    SLICE_X13Y39.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR
    SLICE_X19Y39.SR      net (fanout=3)        1.072   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR
    SLICE_X19Y39.CLK     Trck                  0.325   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly<0>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE
    -------------------------------------------------  ---------------------------
    Total                                      4.668ns (1.622ns logic, 3.046ns route)
                                                       (34.7% logic, 65.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.579ns (data path - clock path skew + uncertainty)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE (FF)
  Data Path Delay:      4.544ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y46.DQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET
    SLICE_X12Y46.C2      net (fanout=8)        0.535   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
    SLICE_X12Y46.C       Tilo                  0.255   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[1].U_LUT
    SLICE_X13Y39.B3      net (fanout=1)        1.070   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<1>
    SLICE_X13Y39.B       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE
    SLICE_X13Y39.A5      net (fanout=4)        0.244   icon_control0<5>
    SLICE_X13Y39.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR
    SLICE_X19Y39.SR      net (fanout=3)        1.072   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR
    SLICE_X19Y39.CLK     Trck                  0.325   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDOUT_dly<0>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_RFDRE
    -------------------------------------------------  ---------------------------
    Total                                      4.544ns (1.623ns logic, 2.921ns route)
                                                       (35.7% logic, 64.3% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE (SLICE_X17Y40.SR), 11 paths
--------------------------------------------------------------------------------
Delay (setup path):     4.744ns (data path - clock path skew + uncertainty)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE (FF)
  Data Path Delay:      4.709ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.AQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
    SLICE_X12Y47.B6      net (fanout=4)        0.796   U_icon_pro/U0/U_ICON/iCORE_ID<0>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X15Y39.B4      net (fanout=10)       1.306   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X15Y39.B       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_LCE
    SLICE_X15Y39.A5      net (fanout=2)        0.236   icon_control0<12>
    SLICE_X15Y39.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_CLEAR
    SLICE_X17Y40.SR      net (fanout=3)        0.807   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR
    SLICE_X17Y40.CLK     Trck                  0.267   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly<0>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE
    -------------------------------------------------  ---------------------------
    Total                                      4.709ns (1.564ns logic, 3.145ns route)
                                                       (33.2% logic, 66.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.693ns (data path - clock path skew + uncertainty)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE (FF)
  Data Path Delay:      4.658ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.CQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET
    SLICE_X12Y47.B2      net (fanout=4)        0.745   U_icon_pro/U0/U_ICON/iCORE_ID<2>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X15Y39.B4      net (fanout=10)       1.306   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X15Y39.B       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_LCE
    SLICE_X15Y39.A5      net (fanout=2)        0.236   icon_control0<12>
    SLICE_X15Y39.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_CLEAR
    SLICE_X17Y40.SR      net (fanout=3)        0.807   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR
    SLICE_X17Y40.CLK     Trck                  0.267   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly<0>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE
    -------------------------------------------------  ---------------------------
    Total                                      4.658ns (1.564ns logic, 3.094ns route)
                                                       (33.6% logic, 66.4% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.468ns (data path - clock path skew + uncertainty)
  Source:               U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE (FF)
  Data Path Delay:      4.433ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC to U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X15Y48.AQ      Tcko                  0.430   U_icon_pro/U0/U_ICON/iSYNC
                                                       U_icon_pro/U0/U_ICON/U_SYNC/U_SYNC
    SLICE_X13Y47.C4      net (fanout=1)        0.559   U_icon_pro/U0/U_ICON/iSYNC
    SLICE_X13Y47.C       Tilo                  0.259   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/U_DATA_VALID
    SLICE_X15Y39.B3      net (fanout=10)       1.357   U_icon_pro/U0/U_ICON/U_CTRL_OUT/iDATA_VALID
    SLICE_X15Y39.B       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[8].U_LCE
    SLICE_X15Y39.A5      net (fanout=2)        0.236   icon_control0<12>
    SLICE_X15Y39.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/din_latched
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_CLEAR
    SLICE_X17Y40.SR      net (fanout=3)        0.807   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iCLR
    SLICE_X17Y40.CLK     Trck                  0.267   U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/iDOUT_dly<0>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_RST/U_ARM_XFER/U_RFDRE
    -------------------------------------------------  ---------------------------
    Total                                      4.433ns (1.474ns logic, 2.959ns route)
                                                       (33.3% logic, 66.7% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 (SLICE_X13Y38.SR), 11 paths
--------------------------------------------------------------------------------
Delay (setup path):     4.599ns (data path - clock path skew + uncertainty)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 (FF)
  Data Path Delay:      4.564ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.AQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
    SLICE_X12Y47.B6      net (fanout=4)        0.796   U_icon_pro/U0/U_ICON/iCORE_ID<0>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X13Y39.B5      net (fanout=10)       0.985   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X13Y39.B       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE
    SLICE_X13Y39.A5      net (fanout=4)        0.244   icon_control0<5>
    SLICE_X13Y39.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR
    SLICE_X13Y38.SR      net (fanout=3)        0.972   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR
    SLICE_X13Y38.CLK     Trck                  0.270   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1
    -------------------------------------------------  ---------------------------
    Total                                      4.564ns (1.567ns logic, 2.997ns route)
                                                       (34.3% logic, 65.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.548ns (data path - clock path skew + uncertainty)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 (FF)
  Data Path Delay:      4.513ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.CQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET
    SLICE_X12Y47.B2      net (fanout=4)        0.745   U_icon_pro/U0/U_ICON/iCORE_ID<2>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X13Y39.B5      net (fanout=10)       0.985   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X13Y39.B       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE
    SLICE_X13Y39.A5      net (fanout=4)        0.244   icon_control0<5>
    SLICE_X13Y39.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR
    SLICE_X13Y38.SR      net (fanout=3)        0.972   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR
    SLICE_X13Y38.CLK     Trck                  0.270   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1
    -------------------------------------------------  ---------------------------
    Total                                      4.513ns (1.567ns logic, 2.946ns route)
                                                       (34.7% logic, 65.3% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.424ns (data path - clock path skew + uncertainty)
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1 (FF)
  Data Path Delay:      4.389ns (Levels of Logic = 3)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y46.DQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[11].I_NE0.U_TARGET
    SLICE_X12Y46.C2      net (fanout=8)        0.535   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
    SLICE_X12Y46.C       Tilo                  0.255   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[1].U_LUT
    SLICE_X13Y39.B3      net (fanout=1)        1.070   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<1>
    SLICE_X13Y39.B       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[1].U_LCE
    SLICE_X13Y39.A5      net (fanout=4)        0.244   icon_control0<5>
    SLICE_X13Y39.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/din_latched
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_CLEAR
    SLICE_X13Y38.SR      net (fanout=3)        0.972   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iCLR
    SLICE_X13Y38.CLK     Trck                  0.270   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/U_DOUT1
    -------------------------------------------------  ---------------------------
    Total                                      4.389ns (1.568ns logic, 2.821ns route)
                                                       (35.7% logic, 64.3% route)

--------------------------------------------------------------------------------

Hold Paths: PATH "TS_J_TO_D_path" TIG;
--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[11].U_iCAP_ADDR (SLICE_X5Y41.D4), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      0.562ns (datapath - clock path skew - uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[11].U_SEL (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[11].U_iCAP_ADDR (FF)
  Data Path Delay:      0.597ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[11].U_SEL to U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[11].U_iCAP_ADDR
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X4Y41.DMUX     Tshcko                0.266   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<4>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[11].U_SEL
    SLICE_X5Y41.D4       net (fanout=2)        0.116   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<12>
    SLICE_X5Y41.CLK      Tah         (-Th)    -0.215   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<11>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[11].U_CAP_ADDR_MUX
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[11].U_iCAP_ADDR
    -------------------------------------------------  ---------------------------
    Total                                      0.597ns (0.481ns logic, 0.116ns route)
                                                       (80.6% logic, 19.4% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR (SLICE_X5Y41.A4), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      0.563ns (datapath - clock path skew - uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR (FF)
  Data Path Delay:      0.598ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL to U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X4Y41.AMUX     Tshcko                0.266   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<4>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[8].U_SEL
    SLICE_X5Y41.A4       net (fanout=2)        0.117   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<9>
    SLICE_X5Y41.CLK      Tah         (-Th)    -0.215   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<11>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_CAP_ADDR_MUX
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[8].U_iCAP_ADDR
    -------------------------------------------------  ---------------------------
    Total                                      0.598ns (0.481ns logic, 0.117ns route)
                                                       (80.4% logic, 19.6% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR (SLICE_X7Y40.B4), 1 path
--------------------------------------------------------------------------------
Delay (hold path):      0.590ns (datapath - clock path skew - uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[5].U_SEL (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR (FF)
  Data Path Delay:      0.625ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    clk_BUFGP rising
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[5].U_SEL to U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X7Y41.BQ       Tcko                  0.198   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<8>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[5].U_SEL
    SLICE_X7Y40.B4       net (fanout=2)        0.212   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<6>
    SLICE_X7Y40.CLK      Tah         (-Th)    -0.215   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/iCAP_ADDR<7>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_CAP_ADDR_MUX
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_INTCAP.F_CAP_ADDR[5].U_iCAP_ADDR
    -------------------------------------------------  ---------------------------
    Total                                      0.625ns (0.413ns logic, 0.212ns route)
                                                       (66.1% logic, 33.9% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: PATH "TS_D_TO_J_path" TIG;

 217 paths analyzed, 199 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors)
--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO (SLICE_X12Y35.A1), 19 paths
--------------------------------------------------------------------------------
Delay (setup path):     4.693ns (data path - clock path skew + uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/G_NS[0].U_NSQ (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO (FF)
  Data Path Delay:      4.658ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         clk_BUFGP rising
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/G_NS[0].U_NSQ to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y34.AQ      Tcko                  0.476   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/NS_dstat<3>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/G_NS[0].U_NSQ
    SLICE_X10Y33.D1      net (fanout=1)        0.991   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/NS_dstat<0>
    SLICE_X10Y33.CMUX    Topdc                 0.402   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DSTAT<4>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DMUX4/U_CS_MUX/I3.U_MUX8/Mmux_O_4
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DMUX4/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f7
    SLICE_X11Y33.A6      net (fanout=1)        0.167   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DSTAT<4>
    SLICE_X11Y33.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/NS_dstat<11>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O118
    SLICE_X12Y35.C1      net (fanout=1)        1.203   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O117
    SLICE_X12Y35.C       Tilo                  0.255   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O124
    SLICE_X12Y35.A1      net (fanout=1)        0.566   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O123
    SLICE_X12Y35.CLK     Tas                   0.339   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O125
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    -------------------------------------------------  ---------------------------
    Total                                      4.658ns (1.731ns logic, 2.927ns route)
                                                       (37.2% logic, 62.8% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.675ns (data path - clock path skew + uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/G_NS[1].U_NSQ (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO (FF)
  Data Path Delay:      4.640ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         clk_BUFGP rising
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/G_NS[1].U_NSQ to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y34.BQ      Tcko                  0.476   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/NS_dstat<3>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/G_NS[1].U_NSQ
    SLICE_X10Y33.D4      net (fanout=1)        0.973   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/NS_dstat<1>
    SLICE_X10Y33.CMUX    Topdc                 0.402   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DSTAT<4>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DMUX4/U_CS_MUX/I3.U_MUX8/Mmux_O_4
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DMUX4/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f7
    SLICE_X11Y33.A6      net (fanout=1)        0.167   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DSTAT<4>
    SLICE_X11Y33.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/NS_dstat<11>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O118
    SLICE_X12Y35.C1      net (fanout=1)        1.203   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O117
    SLICE_X12Y35.C       Tilo                  0.255   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O124
    SLICE_X12Y35.A1      net (fanout=1)        0.566   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O123
    SLICE_X12Y35.CLK     Tas                   0.339   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O125
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    -------------------------------------------------  ---------------------------
    Total                                      4.640ns (1.731ns logic, 2.909ns route)
                                                       (37.3% logic, 62.7% route)

--------------------------------------------------------------------------------
Delay (setup path):     4.671ns (data path - clock path skew + uncertainty)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/G_NS[7].U_NSQ (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO (FF)
  Data Path Delay:      4.636ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         clk_BUFGP rising
  Destination Clock:    icon_control0<0> rising at 0.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/G_NS[7].U_NSQ to U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y34.DMUX    Tshcko                0.535   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/NS_dstat<3>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/G_NS[7].U_NSQ
    SLICE_X10Y33.C2      net (fanout=1)        0.909   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/NS_dstat<7>
    SLICE_X10Y33.CMUX    Tilo                  0.403   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DSTAT<4>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DMUX4/U_CS_MUX/I3.U_MUX8/Mmux_O_3
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DMUX4/U_CS_MUX/I3.U_MUX8/Mmux_O_2_f7
    SLICE_X11Y33.A6      net (fanout=1)        0.167   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/DSTAT<4>
    SLICE_X11Y33.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/NS_dstat<11>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O118
    SLICE_X12Y35.C1      net (fanout=1)        1.203   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O117
    SLICE_X12Y35.C       Tilo                  0.255   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O124
    SLICE_X12Y35.A1      net (fanout=1)        0.566   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O123
    SLICE_X12Y35.CLK     Tas                   0.339   U_ila_pro_0/U0/I_NO_D.U_ILA/iSTAT_DOUT
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_MUX/U_CS_MUX/I1.U_MUX2/Mmux_O125
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_TDO
    -------------------------------------------------  ---------------------------
    Total                                      4.636ns (1.791ns logic, 2.845ns route)
                                                       (38.6% logic, 61.4% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[9].SI_CFG/I_YESLUT6.U_SRLC16E (SLICE_X12Y25.A4), 1 path
--------------------------------------------------------------------------------
Delay (setup path):     3.082ns (data path)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[9].SI_CFG/I_YESLUT6.U_SRLC16E (FF)
  Data Path Delay:      3.082ns (Levels of Logic = 0)
  Source Clock:         clk_BUFGP rising

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG to U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[9].SI_CFG/I_YESLUT6.U_SRLC16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y37.AQ      Tcko                  0.525   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/trigCondIn
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG
    SLICE_X12Y25.A4      net (fanout=17)       2.557   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/trigCondIn
    -------------------------------------------------  ---------------------------
    Total                                      3.082ns (0.525ns logic, 2.557ns route)
                                                       (17.0% logic, 83.0% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[14].SI_CFG/I_YESLUT6.U_SRLC16E (SLICE_X8Y26.D4), 1 path
--------------------------------------------------------------------------------
Delay (setup path):     3.068ns (data path)
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[14].SI_CFG/I_YESLUT6.U_SRLC16E (FF)
  Data Path Delay:      3.068ns (Levels of Logic = 0)
  Source Clock:         clk_BUFGP rising

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG to U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[14].SI_CFG/I_YESLUT6.U_SRLC16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y37.AQ      Tcko                  0.525   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/trigCondIn
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TM/G_NMU[0].U_M/I_MC_NO.U_NO_MC_REG
    SLICE_X8Y26.D4       net (fanout=17)       2.543   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/trigCondIn
    -------------------------------------------------  ---------------------------
    Total                                      3.068ns (0.525ns logic, 2.543ns route)
                                                       (17.1% logic, 82.9% route)

--------------------------------------------------------------------------------

================================================================================
Timing constraint: TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns HIGH 50%;

 2035 paths analyzed, 368 endpoints analyzed, 0 failing endpoints
 0 timing errors detected. (0 setup errors, 0 hold errors, 0 component switching limit errors)
 Minimum period is   7.982ns.
--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_TDO_reg (SLICE_X13Y48.C6), 31 paths
--------------------------------------------------------------------------------
Slack (setup path):     22.018ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18 (RAM)
  Destination:          U_icon_pro/U0/U_ICON/U_TDO_reg (FF)
  Requirement:          30.000ns
  Data Path Delay:      7.947ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18 to U_icon_pro/U0/U_ICON/U_TDO_reg
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y24.DOA0    Trcko_DOA             2.100   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18
    SLICE_X18Y44.D1      net (fanout=1)        1.370   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_data<0>
    SLICE_X18Y44.CMUX    Topdc                 0.402   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_5_f7
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_7
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_5_f7
    SLICE_X9Y44.A5       net (fanout=1)        0.893   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_5_f7
    SLICE_X9Y44.A        Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_col_addr_dly<3>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_col_addr_dly<3>
    SLICE_X11Y38.B5      net (fanout=1)        0.913   U_ila_pro_0/U0/I_NO_D.U_ILA/iDATA_DOUT
    SLICE_X11Y38.BMUX    Tilo                  0.337   U_ila_pro_0/U0/I_NO_D.U_ILA/iTRIGGER
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_DOUT
    SLICE_X13Y48.C6      net (fanout=1)        1.300   icon_control0<3>
    SLICE_X13Y48.CLK     Tas                   0.373   U_icon_pro/U0/U_ICON/iTDO
                                                       U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O11
                                                       U_icon_pro/U0/U_ICON/U_TDO_reg
    -------------------------------------------------  ---------------------------
    Total                                      7.947ns (3.471ns logic, 4.476ns route)
                                                       (43.7% logic, 56.3% route)

--------------------------------------------------------------------------------
Slack (setup path):     22.257ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18 (RAM)
  Destination:          U_icon_pro/U0/U_ICON/U_TDO_reg (FF)
  Requirement:          30.000ns
  Data Path Delay:      7.708ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18 to U_icon_pro/U0/U_ICON/U_TDO_reg
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y24.DOA2    Trcko_DOA             2.100   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18
    SLICE_X18Y44.D3      net (fanout=1)        1.131   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_data<2>
    SLICE_X18Y44.CMUX    Topdc                 0.402   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_5_f7
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_7
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_5_f7
    SLICE_X9Y44.A5       net (fanout=1)        0.893   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_5_f7
    SLICE_X9Y44.A        Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_col_addr_dly<3>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_col_addr_dly<3>
    SLICE_X11Y38.B5      net (fanout=1)        0.913   U_ila_pro_0/U0/I_NO_D.U_ILA/iDATA_DOUT
    SLICE_X11Y38.BMUX    Tilo                  0.337   U_ila_pro_0/U0/I_NO_D.U_ILA/iTRIGGER
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_DOUT
    SLICE_X13Y48.C6      net (fanout=1)        1.300   icon_control0<3>
    SLICE_X13Y48.CLK     Tas                   0.373   U_icon_pro/U0/U_ICON/iTDO
                                                       U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O11
                                                       U_icon_pro/U0/U_ICON/U_TDO_reg
    -------------------------------------------------  ---------------------------
    Total                                      7.708ns (3.471ns logic, 4.237ns route)
                                                       (45.0% logic, 55.0% route)

--------------------------------------------------------------------------------
Slack (setup path):     22.348ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18 (RAM)
  Destination:          U_icon_pro/U0/U_ICON/U_TDO_reg (FF)
  Requirement:          30.000ns
  Data Path Delay:      7.617ns (Levels of Logic = 4)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18 to U_icon_pro/U0/U_ICON/U_TDO_reg
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    RAMB16_X1Y24.DOA1    Trcko_DOA             2.100   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18
    SLICE_X18Y44.D5      net (fanout=1)        1.040   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_data<1>
    SLICE_X18Y44.CMUX    Topdc                 0.402   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_5_f7
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_7
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_5_f7
    SLICE_X9Y44.A5       net (fanout=1)        0.893   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_COL_MUX/I4.U_MUX16/Mmux_O_5_f7
    SLICE_X9Y44.A        Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_col_addr_dly<3>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_col_addr_dly<3>
    SLICE_X11Y38.B5      net (fanout=1)        0.913   U_ila_pro_0/U0/I_NO_D.U_ILA/iDATA_DOUT
    SLICE_X11Y38.BMUX    Tilo                  0.337   U_ila_pro_0/U0/I_NO_D.U_ILA/iTRIGGER
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_DOUT
    SLICE_X13Y48.C6      net (fanout=1)        1.300   icon_control0<3>
    SLICE_X13Y48.CLK     Tas                   0.373   U_icon_pro/U0/U_ICON/iTDO
                                                       U_icon_pro/U0/U_ICON/U_TDO_MUX/U_CS_MUX/I4.U_MUX16/Mmux_O11
                                                       U_icon_pro/U0/U_ICON/U_TDO_reg
    -------------------------------------------------  ---------------------------
    Total                                      7.617ns (3.471ns logic, 4.146ns route)
                                                       (45.6% logic, 54.4% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E (SLICE_X8Y26.CE), 11 paths
--------------------------------------------------------------------------------
Slack (setup path):     24.459ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E (FF)
  Requirement:          30.000ns
  Data Path Delay:      5.506ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y46.BQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET
    SLICE_X13Y38.C2      net (fanout=8)        1.698   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<9>
    SLICE_X13Y38.C       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[15].U_LUT
    SLICE_X13Y38.A2      net (fanout=1)        0.542   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<15>
    SLICE_X13Y38.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
    SLICE_X8Y26.CE       net (fanout=14)       1.985   icon_control0<19>
    SLICE_X8Y26.CLK      Tceck                 0.238   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/and_out<14>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E
    -------------------------------------------------  ---------------------------
    Total                                      5.506ns (1.281ns logic, 4.225ns route)
                                                       (23.3% logic, 76.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     24.615ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E (FF)
  Requirement:          30.000ns
  Data Path Delay:      5.350ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.AQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
    SLICE_X12Y47.B6      net (fanout=4)        0.796   U_icon_pro/U0/U_ICON/iCORE_ID<0>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X13Y38.A3      net (fanout=10)       1.293   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X13Y38.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
    SLICE_X8Y26.CE       net (fanout=14)       1.985   icon_control0<19>
    SLICE_X8Y26.CLK      Tceck                 0.238   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/and_out<14>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E
    -------------------------------------------------  ---------------------------
    Total                                      5.350ns (1.276ns logic, 4.074ns route)
                                                       (23.9% logic, 76.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     24.666ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E (FF)
  Requirement:          30.000ns
  Data Path Delay:      5.299ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.CQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET
    SLICE_X12Y47.B2      net (fanout=4)        0.745   U_icon_pro/U0/U_ICON/iCORE_ID<2>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X13Y38.A3      net (fanout=10)       1.293   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X13Y38.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
    SLICE_X8Y26.CE       net (fanout=14)       1.985   icon_control0<19>
    SLICE_X8Y26.CLK      Tceck                 0.238   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/and_out<14>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[13].SI_CFG/I_YESLUT6.U_SRLC16E
    -------------------------------------------------  ---------------------------
    Total                                      5.299ns (1.276ns logic, 4.023ns route)
                                                       (24.1% logic, 75.9% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E (SLICE_X8Y26.CE), 11 paths
--------------------------------------------------------------------------------
Slack (setup path):     24.459ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E (FF)
  Requirement:          30.000ns
  Data Path Delay:      5.506ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y46.BQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<11>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[9].I_NE0.U_TARGET
    SLICE_X13Y38.C2      net (fanout=8)        1.698   U_icon_pro/U0/U_ICON/U_CMD/iTARGET<9>
    SLICE_X13Y38.C       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_COMMAND_SEL/I4.FI[15].U_LUT
    SLICE_X13Y38.A2      net (fanout=1)        0.542   U_icon_pro/U0/U_ICON/iCOMMAND_SEL<15>
    SLICE_X13Y38.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
    SLICE_X8Y26.CE       net (fanout=14)       1.985   icon_control0<19>
    SLICE_X8Y26.CLK      Tceck                 0.238   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/and_out<14>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E
    -------------------------------------------------  ---------------------------
    Total                                      5.506ns (1.281ns logic, 4.225ns route)
                                                       (23.3% logic, 76.7% route)

--------------------------------------------------------------------------------
Slack (setup path):     24.615ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E (FF)
  Requirement:          30.000ns
  Data Path Delay:      5.350ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.AQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[12].I_NE0.U_TARGET
    SLICE_X12Y47.B6      net (fanout=4)        0.796   U_icon_pro/U0/U_ICON/iCORE_ID<0>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X13Y38.A3      net (fanout=10)       1.293   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X13Y38.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
    SLICE_X8Y26.CE       net (fanout=14)       1.985   icon_control0<19>
    SLICE_X8Y26.CLK      Tceck                 0.238   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/and_out<14>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E
    -------------------------------------------------  ---------------------------
    Total                                      5.350ns (1.276ns logic, 4.074ns route)
                                                       (23.9% logic, 76.1% route)

--------------------------------------------------------------------------------
Slack (setup path):     24.666ns (requirement - (data path - clock path skew + uncertainty))
  Source:               U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E (FF)
  Requirement:          30.000ns
  Data Path Delay:      5.299ns (Levels of Logic = 2)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 0.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.035ns

  Clock Uncertainty:          0.035ns  ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
    Total System Jitter (TSJ):  0.070ns
    Total Input Jitter (TIJ):   0.000ns
    Discrete Jitter (DJ):       0.000ns
    Phase Error (PE):           0.000ns

  Maximum Data Path at Slow Process Corner: U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET to U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y47.CQ      Tcko                  0.525   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/G_TARGET[14].I_NE0.U_TARGET
    SLICE_X12Y47.B2      net (fanout=4)        0.745   U_icon_pro/U0/U_ICON/iCORE_ID<2>
    SLICE_X12Y47.B       Tilo                  0.254   U_icon_pro/U0/U_ICON/iCORE_ID<3>
                                                       U_icon_pro/U0/U_ICON/U_CMD/U_CORE_ID_SEL/I4.FI[0].U_LUT
    SLICE_X13Y38.A3      net (fanout=10)       1.293   U_icon_pro/U0/U_ICON/iCORE_ID_SEL<0>
    SLICE_X13Y38.A       Tilo                  0.259   U_ila_pro_0/U0/I_NO_D.U_ILA/U_STAT/U_DSL1/iDIN<1>
                                                       U_icon_pro/U0/U_ICON/U_CTRL_OUT/F_NCP[0].F_CMD[15].U_LCE
    SLICE_X8Y26.CE       net (fanout=14)       1.985   icon_control0<19>
    SLICE_X8Y26.CLK      Tceck                 0.238   U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/and_out<14>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_TRIG/U_TC/I_TSEQ_EQ1.I_TSEQ_SIMPLE/U_STATES[15].SI_CFG/I_YESLUT6.U_SRLC16E
    -------------------------------------------------  ---------------------------
    Total                                      5.299ns (1.276ns logic, 4.023ns route)
                                                       (24.1% logic, 75.9% route)

--------------------------------------------------------------------------------

Hold Paths: TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns HIGH 50%;
--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL (SLICE_X4Y41.DX), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.446ns (requirement - (clock path skew + uncertainty - data path))
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.446ns (Levels of Logic = 0)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 30.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL to U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X4Y41.CQ       Tcko                  0.234   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<4>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[2].U_SEL
    SLICE_X4Y41.DX       net (fanout=2)        0.171   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<3>
    SLICE_X4Y41.CLK      Tckdi       (-Th)    -0.041   U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/cfg_data_vec<4>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_G2_SQ.U_CAPCTRL/U_CAP_ADDRGEN/I_0_TO_64K.F_SEL[3].U_SEL
    -------------------------------------------------  ---------------------------
    Total                                      0.446ns (0.275ns logic, 0.171ns route)
                                                       (61.7% logic, 38.3% route)

--------------------------------------------------------------------------------

Paths for end point U_icon_pro/U0/U_ICON/U_STAT/U_TDO (SLICE_X13Y48.B6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.474ns (requirement - (clock path skew + uncertainty - data path))
  Source:               U_icon_pro/U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_FDRE (FF)
  Destination:          U_icon_pro/U0/U_ICON/U_STAT/U_TDO (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.474ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 30.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: U_icon_pro/U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_FDRE to U_icon_pro/U0/U_ICON/U_STAT/U_TDO
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X12Y48.AQ      Tcko                  0.234   U_icon_pro/U0/U_ICON/U_STAT/iSTAT_CNT<3>
                                                       U_icon_pro/U0/U_ICON/U_STAT/U_STAT_CNT/G[0].U_FDRE
    SLICE_X13Y48.B6      net (fanout=2)        0.025   U_icon_pro/U0/U_ICON/U_STAT/iSTAT_CNT<0>
    SLICE_X13Y48.CLK     Tah         (-Th)    -0.215   U_icon_pro/U0/U_ICON/iTDO
                                                       U_icon_pro/U0/U_ICON/U_STAT/U_TDO_next
                                                       U_icon_pro/U0/U_ICON/U_STAT/U_TDO
    -------------------------------------------------  ---------------------------
    Total                                      0.474ns (0.449ns logic, 0.025ns route)
                                                       (94.7% logic, 5.3% route)

--------------------------------------------------------------------------------

Paths for end point U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_ROW_ADDR/G[11].U_FDRE (SLICE_X10Y46.D6), 1 path
--------------------------------------------------------------------------------
Slack (hold path):      0.476ns (requirement - (clock path skew + uncertainty - data path))
  Source:               U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_ROW_ADDR/G[11].U_FDRE (FF)
  Destination:          U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_ROW_ADDR/G[11].U_FDRE (FF)
  Requirement:          0.000ns
  Data Path Delay:      0.476ns (Levels of Logic = 1)
  Clock Path Skew:      0.000ns
  Source Clock:         icon_control0<0> rising at 30.000ns
  Destination Clock:    icon_control0<0> rising at 30.000ns
  Clock Uncertainty:    0.000ns

  Minimum Data Path at Fast Process Corner: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_ROW_ADDR/G[11].U_FDRE to U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_ROW_ADDR/G[11].U_FDRE
    Location             Delay type         Delay(ns)  Physical Resource
                                                       Logical Resource(s)
    -------------------------------------------------  -------------------
    SLICE_X10Y46.DQ      Tcko                  0.200   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_row_addr<11>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_ROW_ADDR/G[11].U_FDRE
    SLICE_X10Y46.D6      net (fanout=4)        0.039   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_row_addr<11>
    SLICE_X10Y46.CLK     Tah         (-Th)    -0.237   U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_row_addr<11>
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/rd_row_addr<11>_rt
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_ROW_ADDR/G[11].U_XORCY
                                                       U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RD_ROW_ADDR/G[11].U_FDRE
    -------------------------------------------------  ---------------------------
    Total                                      0.476ns (0.437ns logic, 0.039ns route)
                                                       (91.8% logic, 8.2% route)

--------------------------------------------------------------------------------

Component Switching Limit Checks: TS_J_CLK = PERIOD TIMEGRP "J_CLK" 30 ns HIGH 50%;
--------------------------------------------------------------------------------
Slack: 26.430ns (period - min period limit)
  Period: 30.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18/CLKA
  Logical resource: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[0].u_ramb18/U_RAMB18/CLKA
  Location pin: RAMB16_X1Y24.CLKA
  Clock network: icon_control0<0>
--------------------------------------------------------------------------------
Slack: 26.430ns (period - min period limit)
  Period: 30.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B9KGT0.u_ramb9/U_RAMB9/CLKAWRCLK
  Logical resource: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B9KGT0.u_ramb9/U_RAMB9/CLKAWRCLK
  Location pin: RAMB8_X0Y22.CLKAWRCLK
  Clock network: icon_control0<0>
--------------------------------------------------------------------------------
Slack: 26.430ns (period - min period limit)
  Period: 30.000ns
  Min period limit: 3.570ns (280.112MHz) (Trper_CLKA(Fmax))
  Physical resource: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[1].u_ramb18/U_RAMB18/CLKA
  Logical resource: U_ila_pro_0/U0/I_NO_D.U_ILA/U_CAPSTOR/I_CASE1.I_YES_TB.U_TRACE_BUFFER/U_RAM/I_S6.U_CS_BRAM_CASCADE_S6/I_DEPTH_LTEQ_16K.U_SBRAM_0/I_B18KGT0.G_RAMB18[1].u_ramb18/U_RAMB18/CLKA
  Location pin: RAMB16_X1Y22.CLKA
  Clock network: icon_control0<0>
--------------------------------------------------------------------------------


All constraints were met.


Data Sheet report:
-----------------
No constraints were found to generate data for the Data Sheet Report section.
Use the Advanced Analysis (-a) option or generate global constraints for each
clock, its pad to setup and clock to pad paths, and a pad to pad constraint.

Timing summary:
---------------

Timing errors: 0  Score: 0  (Setup/Max: 0, Hold: 0)

Constraints cover 2679 paths, 0 nets, and 774 connections

Design statistics:
   Minimum period:   7.982ns{1}   (Maximum frequency: 125.282MHz)
   Maximum path delay from/to any node:   3.299ns


------------------------------------Footnotes-----------------------------------
1)  The minimum period statistic assumes all single cycle delays.

Analysis completed Mon Dec 12 15:24:08 2011 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 207 MB



