zhongzhilvbo Project Status (05/06/2012 - 18:39:52)
Project File: | zhongzhilvbo.xise | Parser Errors: | No Errors
Module Name: | zhongzhilvbo | Implementation State: | Synthesized
Target Device: | xc6slx9-3tqg144 | Errors: | No Errors
Product Version: | ISE 13.2 | Warnings: | 1 Warning (1 new)
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slice Registers | 104 | 11440 | 0%
Number of Slice LUTs | 105 | 5720 | 1%
Number of fully used LUT-FF pairs | 54 | 155 | 34%
Number of bonded IOBs | 82 | 102 | 80%
Number of BUFG/BUFGCTRLs | 1 | 16 | 6%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | 周日 五月 6 18:39:51 2012 | 0 | 1 Warning (1 new) | 0
Translation Report | Out of Date | 周二 六月 2 15:46:01 2009 |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated

Date Generated: 05/06/2012 - 18:39:52