##############################################################
#
# Xilinx Core Generator version K.39
# Date: Tue Jun 02 06:36:32 2009
#
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#
#  This file contains the customisation parameters for a
#  Xilinx CORE Generator IP GUI. It is strongly recommended
#  that you do not manually alter this file as it may cause
#  unexpected and unsupported behavior.
#
##############################################################
#
# BEGIN Project Options
SET addpads = False
SET asysymbol = True
SET busformat = BusFormatAngleBracketNotRipped
SET createndf = False
SET designentry = VHDL
SET device = xc3s500e
SET devicefamily = spartan3e
SET flowvendor = Foundation_iSE
SET formalverification = False
SET foundationsym = False
SET implementationfiletype = Ngc
SET package = fg320
SET removerpms = False
SET simulationfiles = Behavioral
SET speedgrade = -4
SET verilogsim = True
SET vhdlsim = True
# END Project Options
# BEGIN Select
SELECT Comparator family Xilinx,_Inc. 9.0
# END Select
# BEGIN Parameters
CSET aclr=false
CSET ainitval=0
CSET aset=false
CSET ce=false
CSET cepriority=Sync_Overrides_CE
CSET component_name=compare8
CSET constantbport=false
CSET constantbportvalue=0000000000000000
CSET datatype=Unsigned
CSET nonregisteredoutput=true
CSET operation=gt
CSET pipelinestages=0
CSET radix=2
CSET registeredoutput=false
CSET sclr=false
CSET sset=false
CSET syncctrlpriority=Reset_Overrides_Set
CSET width=8
# END Parameters
GENERATE
# CRC: c9644b74

