CoreGen has not been configured with any user repositories.
CoreGen has been configured with the following Xilinx repositories:
 - 'G:\Software\ISE_DS\ISE\coregen\' [using existing xil_index.xml]
INFO:encore:314 - Created non-GUI application for batch mode execution.
Wrote CGP file for project 'coregen'.
INFO:sim - Generating component instance 'icon_pro' of
   'xilinx.com:ip:chipscope_icon:1.05.a' from
   'G:\Software\ISE_DS\ISE\coregen\iprepo\Chipscope\pcores\chipscope_icon_v1_05_
   a\chipscope_icon_v1_05_a.xcd'.
Resolving generic values...
Finished resolving generic values.
Generating IP...
Gathering HDL files for icon_pro root...
Creating XST project for icon_pro...
Creating XST script file for icon_pro...
Creating XST instantiation file for icon_pro...
Running XST for icon_pro...
XST: HDL Parsing
XST: HDL Elaboration
XST: HDL Synthesis
XST: Advanced HDL Synthesis
XST: Low Level Synthesis
XST: Design Summary
Generating VHDL wrapper
Not generating Verilog wrapper
Creating ISE instantiation template for icon_pro...
Skipping Verilog instantiation template for icon_pro...
Finished Generation.
Generating IP instantiation template...
Generating metadata file...
Generating ISE project...
Generating README file...
Generating FLIST file...
INFO:sim - Finished FLIST file generation.
Moving files to output directory...
Finished moving files to output directory
Saved CGP file for project 'coregen'.
