CoreGen has not been configured with any user repositories.
CoreGen has been configured with the following Xilinx repositories:
 - 'G:\Software\ISE_DS\ISE\coregen\' [reloaded]
INFO:sim - Generating component instance 'adder' of
   'xilinx.com:ip:c_addsub:11.0' from
   'G:\Software\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\c_addsub_v11_
   0\component.xml'.
WARNING:sim - Verilog simulation file type 'Behavioral' is not valid for this
   core. Overriding with simulation file type 'Structural'.
Resolving generics for 'adder'...
WARNING:sim - Verilog simulation file type 'Behavioral' is not valid for this
   core. Overriding with simulation file type 'Structural'.
Applying external generics to 'adder'...
Delivering associated files for 'adder'...
Generating implementation netlist for 'adder'...
INFO:sim - Pre-processing HDL files for 'adder'...
Running synthesis for 'adder'
Writing VEO instantiation template for 'adder'...
WARNING:sim - Verilog simulation file type 'Behavioral' is not valid for this
   core. Overriding with simulation file type 'Structural'.
Writing Verilog structural simulation model for 'adder'...
WARNING:sim - Verilog simulation file type 'Behavioral' is not valid for this
   core. Overriding with simulation file type 'Structural'.
Delivered 2 files into directory
G:/Work/FPGA_CD/chapter4/exp4_1/ipcore_dir/tmp/_cg/adder
Generating ASY schematic symbol...
Generating SYM schematic symbol for 'adder'...
Generating metadata file...
Generating metadata file...
Generating ISE project...
Generating README file...
Generating FLIST file...
INFO:sim - Finished FLIST file generation.
Launching README viewer...
Moving files to output directory...
Finished moving files to output directory
Wrote CGP file for project 'adder'.
