test Project Status
Project File: | exp4_2.xise | Parser Errors: | No Errors
Module Name: | test | Implementation State: | Synthesized
Target Device: | xc6slx9-3tqg144 | Errors: | No Errors
Product Version: | ISE 13.2 | Warnings: | 1 Warning (1 new)
Design Goal: | Balanced | Routing Results: |
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: |
Environment: | System Settings | Final Timing Score: |

Device Utilization Summary (estimated values) | [-]
Logic Utilization | Used | Available | Utilization
Number of Slice LUTs | 9 | 5720 | 0%
Number of fully used LUT-FF pairs | 0 | 9 | 0%
Number of bonded IOBs | 17 | 102 | 16%
Number of BUFG/BUFGCTRLs | 1 | 16 | 6%

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | 周日 五月 6 18:25:39 2012 | 0 | 1 Warning (1 new) | 0
Translation Report |  |  |  |  |
Map Report |  |  |  |  |
Place and Route Report |  |  |  |  |
Power Report |  |  |  |  |
Post-PAR Static Timing Report |  |  |  |  |
Bitgen Report |  |  |  |  |

Secondary Reports | [-]
Report Name | Status | Generated
ISIM Simulator Log | Current | 周日 五月 6 18:31:13 2012

Date Generated: 05/06/2012 - 18:33:01