D:/Xilinx/10.1/ISE/verilog/src/glbl.v
N:/K.39/rtf/verilog/src/unisims/MUXCY.v
N:/K.39/rtf/verilog/src/unisims/LUT2.v
N:/K.39/rtf/verilog/src/unisims/GND.v
N:/K.39/rtf/verilog/src/unisims/VCC.v
E:/ISE/zhongzhilvbo/compare8.v
E:/ISE/zhongzhilvbo/zhongzhilvbo.v
E:/ISE/zhongzhilvbo/tb_midfilt2_demo.v
