counter Project Status
Project File: | exp4_6.xise | Parser Errors: | No Errors
Module Name: | counter | Implementation State: | Programming File Generated
Target Device: | xc6slx9-2tqg144 | Errors: | No Errors
Product Version: | ISE 13.2 | Warnings: | 5 Warnings (5 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 258 | 11,440 | 2% |
Number used as Flip Flops | 257 |  |  |
Number used as Latches | 1 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 0 |  |  |
Number of Slice LUTs | 235 | 5,720 | 4% |
Number used as logic | 145 | 5,720 | 2% |
Number using O6 output only | 78 |  |  |
Number using O5 output only | 50 |  |  |
Number using O5 and O6 | 17 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 61 | 1,440 | 4% |
Number used as Dual Port RAM | 0 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 61 |  |  |
Number using O6 output only | 59 |  |  |
Number using O5 output only | 1 |  |  |
Number using O5 and O6 | 1 |  |  |
Number used exclusively as route-thrus | 29 |  |  |
Number with same-slice register load | 23 |  |  |
Number with same-slice carry load | 6 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 130 | 1,430 | 9% |
Number of LUT Flip Flop pairs used | 316 |  |  |
Number with an unused Flip Flop | 84 | 316 | 26% |
Number with an unused LUT | 81 | 316 | 25% |
Number of fully used LUT-FF pairs | 151 | 316 | 47% |
Number of unique control sets | 53 |  |  |
Number of slice register sites lost to control set restrictions | 272 | 11,440 | 2% |
Number of bonded IOBs | 9 | 102 | 8% |
Number of LOCed IOBs | 1 | 9 | 11% |
Number of RAMB16BWERs | 2 | 32 | 6% |
Number of RAMB8BWERs | 1 | 64 | 1% |
Number of BUFIO2/BUFIO2_2CLKs | 0 | 32 | 0% |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 2 | 16 | 12% |
Number used as BUFGs | 2 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 0 | 200 | 0% |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 0 | 200 | 0% |
Number of OLOGIC2/OSERDES2s | 0 | 200 | 0% |
Number of BSCANs | 1 | 4 | 25% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 0 | 4 | 0% |
Number of DSP48A1s | 0 | 16 | 0% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 0 | 2 | 0% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 0 | 2 | 0% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Number of RPM macros | 9 |  |  |
Average Fanout of Non-Clock Nets | 2.93 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | 周一 十二月 12 15:15:53 2011 | 0 | 1 Warning (1 new) | 0
Translation Report | Current | 周一 十二月 12 15:23:32 2011 | 0 | 0 | 0
Map Report | Current | 周一 十二月 12 15:23:50 2011 | 0 | 2 Warnings (2 new) | 8 Infos (8 new)
Place and Route Report | Current | 周一 十二月 12 15:24:01 2011 | 0 | 0 | 1 Info (1 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | 周一 十二月 12 15:24:08 2011 | 0 | 0 | 2 Infos (2 new)
Bitgen Report | Current | 周一 十二月 12 15:24:19 2011 | 0 | 2 Warnings (2 new) | 1 Info (1 new)

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | 周一 十二月 12 15:24:19 2011
WebTalk Log File | Current | 周一 十二月 12 15:24:23 2011

Date Generated: 05/06