Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 
 
Software Version and Target Device
Product Version: ISE:13.2 (ISE) - O.61xd Target Family: Spartan6
OS Platform: NT64 Target Device: xc6slx9
Project ID (random number) f588f00868f0480eb8e4b89866a19951.6722449814024B449CE8FDE2FE8F11EF.1 Target Package: tqg144
Registration ID 135256_15690819_173552794_661 Target Speed: -2
Date Generated 2011-12-12T15:24:19 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i3-2310M CPU @ 2.10GHz CPU Speed 2095 MHz
OS Name Microsoft Windows 7 , 64-bit OS Release major release (build 7600)
CPU Name Intel(R) Core(TM) i3-2310M CPU @ 2.10GHz CPU Speed 2095 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
Counters=1
  • 8-bit up counter=1
 		MiscellaneousStatistics
  • AGG_BONDED_IO=9
  • AGG_IO=9
  • AGG_LOCED_IO=1
  • AGG_SLICE=130
  • NUM_BONDED_IOB=9
  • NUM_BSCAN=1
  • NUM_BSFULL=151
  • NUM_BSLUTONLY=84
  • NUM_BSREGONLY=81
  • NUM_BSUSED=316
  • NUM_BUFG=2
  • NUM_LOCED_IOB=1
  • NUM_LOGIC_O5ANDO6=17
  • NUM_LOGIC_O5ONLY=50
  • NUM_LOGIC_O6ONLY=78
  • NUM_LUT_RT_DRIVES_CARRY4=6
  • NUM_LUT_RT_DRIVES_FLOP=23
  • NUM_LUT_RT_EXO5=23
  • NUM_LUT_RT_EXO6=6
  • NUM_LUT_RT_O5=3
  • NUM_LUT_RT_O6=50
  • NUM_RAMB16BWER=2
  • NUM_RAMB8BWER=1
  • NUM_RPM=9
  • NUM_SLICEL=24
  • NUM_SLICEM=28
  • NUM_SLICEX=78
  • NUM_SLICE_CARRY4=25
  • NUM_SLICE_CONTROLSET=53
  • NUM_SLICE_CYINIT=317
  • NUM_SLICE_F7MUX=10
  • NUM_SLICE_F8MUX=2
  • NUM_SLICE_FF=257
  • NUM_SLICE_LATCH=1
  • NUM_SLICE_UNUSEDCTRL=6
  • NUM_SRL_O5ANDO6=1
  • NUM_SRL_O5ONLY=1
  • NUM_SRL_O6ONLY=59
  • NUM_UNUSABLE_FF_BELS=272
  • Xilinx Core chipscope_icon_v1_05_a, Xilinx CORE Generator 13.2=1
  • Xilinx Core chipscope_ila_v1_04_a, Xilinx CORE Generator 13.2=1
 		NetStatistics
  • NumNets_Active=420
  • NumNets_Gnd=1
  • NumNets_Vcc=1
  • NumNodesOfType_Active_BOUNCEACROSS=14
  • NumNodesOfType_Active_BOUNCEIN=75
  • NumNodesOfType_Active_BUFGOUT=2
  • NumNodesOfType_Active_BUFHINP2OUT=12
  • NumNodesOfType_Active_CLKPIN=124
  • NumNodesOfType_Active_CLKPINFEED=17
  • NumNodesOfType_Active_CNTRLPIN=130
  • NumNodesOfType_Active_DOUBLE=479
  • NumNodesOfType_Active_GENERIC=9
  • NumNodesOfType_Active_GLOBAL=73
  • NumNodesOfType_Active_INPUT=148
  • NumNodesOfType_Active_IOBIN2OUT=8
  • NumNodesOfType_Active_IOBOUTPUT=8
  • NumNodesOfType_Active_LUTINPUT=607
  • NumNodesOfType_Active_OUTBOUND=413
  • NumNodesOfType_Active_OUTPUT=431
  • NumNodesOfType_Active_PADINPUT=8
  • NumNodesOfType_Active_PADOUTPUT=1
  • NumNodesOfType_Active_PINBOUNCE=387
  • NumNodesOfType_Active_PINFEED=910
  • NumNodesOfType_Active_QUAD=219
  • NumNodesOfType_Active_REGINPUT=143
  • NumNodesOfType_Active_SINGLE=803
  • NumNodesOfType_Gnd_BOUNCEIN=22
  • NumNodesOfType_Gnd_HGNDOUT=14
  • NumNodesOfType_Gnd_INPUT=17
  • NumNodesOfType_Gnd_LUTINPUT=8
  • NumNodesOfType_Gnd_PINBOUNCE=30
  • NumNodesOfType_Gnd_PINFEED=23
  • NumNodesOfType_Gnd_REGINPUT=17
  • NumNodesOfType_Vcc_CNTRLPIN=3
  • NumNodesOfType_Vcc_HVCCOUT=62
  • NumNodesOfType_Vcc_INPUT=189
  • NumNodesOfType_Vcc_KVCCOUT=43
  • NumNodesOfType_Vcc_LUTINPUT=234
  • NumNodesOfType_Vcc_PINBOUNCE=26
  • NumNodesOfType_Vcc_PINFEED=404
  • NumNodesOfType_Vcc_REGINPUT=4
 SiteStatistics
  • BUFG-BUFGMUX=2
  • IOB-IOBM=4
  • IOB-IOBS=5
  • SLICEL-SLICEM=10
  • SLICEX-SLICEL=11
  • SLICEX-SLICEM=21
 		SiteSummary
  • BSCAN=1
  • BSCAN_BSCAN=1
  • BUFG=2
  • BUFG_BUFG=2
  • CARRY4=25
  • FF_SR=27
  • HARD0=1
  • HARD1=10
  • IOB=9
  • IOB_IMUX=1
  • IOB_INBUF=1
  • IOB_OUTBUF=8
  • LUT5=93
  • LUT6=151
  • LUT_OR_MEM5=2
  • LUT_OR_MEM6=60
  • PAD=9
  • RAMB16BWER=2
  • RAMB16BWER_RAMB16BWER=2
  • RAMB8BWER=1
  • RAMB8BWER_RAMB8BWER=1
  • REG_SR=231
  • SELMUX2_1=12
  • SLICEL=24
  • SLICEM=28
  • SLICEX=78
 
Configuration Data
BSCAN_BSCAN
  • JTAG_CHAIN=[1:1]
  • JTAG_TEST=[0:1]
 FF_SR
  • CK=[CK:27] [CK_INV:0]
  • SRINIT=[SRINIT0:19] [SRINIT1:8]
  • SYNC_ATTR=[ASYNC:14] [SYNC:13]
 IOB_OUTBUF
  • DRIVEATTRBOX=[12:8]
  • SLEW=[SLOW:8]
  • SUSPEND=[3STATE:8]
 LUT_OR_MEM5
  • CLK=[CLK:2] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:2]
  • RAMMODE=[SRL16:2]
 LUT_OR_MEM6
  • CLK=[CLK:60] [CLK_INV:0]
  • LUT_OR_MEM=[RAM:60]
  • RAMMODE=[SRL16:31] [SRL32:29]
 RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • ENB=[ENB_INV:0] [ENB:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEB=[REGCEB_INV:0] [REGCEB:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:2] [WEB0_INV:0]
  • WEB1=[WEB1:2] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:0]
 RAMB16BWER_RAMB16BWER
  • CLKA=[CLKA_INV:0] [CLKA:2]
  • CLKB=[CLKB_INV:0] [CLKB:2]
  • DATA_WIDTH_A=[4:2]
  • DATA_WIDTH_B=[4:2]
  • DOA_REG=[0:2]
  • DOB_REG=[0:2]
  • ENA=[ENA_INV:0] [ENA:2]
  • ENB=[ENB_INV:0] [ENB:2]
  • EN_RSTRAM_A=[FALSE:2]
  • EN_RSTRAM_B=[FALSE:2]
  • RAM_MODE=[TDP:2]
  • REGCEA=[REGCEA_INV:0] [REGCEA:2]
  • REGCEB=[REGCEB_INV:0] [REGCEB:2]
  • RSTA=[RSTA:2] [RSTA_INV:0]
  • RSTB=[RSTB:2] [RSTB_INV:0]
  • RSTTYPE=[SYNC:2]
  • RST_PRIORITY_A=[CE:2]
  • RST_PRIORITY_B=[CE:2]
  • WEA0=[WEA0:2] [WEA0_INV:0]
  • WEA1=[WEA1:2] [WEA1_INV:0]
  • WEA2=[WEA2:2] [WEA2_INV:0]
  • WEA3=[WEA3_INV:0] [WEA3:2]
  • WEB0=[WEB0:2] [WEB0_INV:0]
  • WEB1=[WEB1:2] [WEB1_INV:0]
  • WEB2=[WEB2_INV:0] [WEB2:2]
  • WEB3=[WEB3:2] [WEB3_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:2]
  • WRITE_MODE_B=[WRITE_FIRST:2]
 RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
 RAMB8BWER_RAMB8BWER
  • CLKAWRCLK=[CLKAWRCLK:1] [CLKAWRCLK_INV:0]
  • CLKBRDCLK=[CLKBRDCLK_INV:0] [CLKBRDCLK:1]
  • DATA_WIDTH_A=[2:1]
  • DATA_WIDTH_B=[2:1]
  • DOA_REG=[0:1]
  • DOB_REG=[0:1]
  • ENAWREN=[ENAWREN:1] [ENAWREN_INV:0]
  • ENBRDEN=[ENBRDEN_INV:0] [ENBRDEN:1]
  • EN_RSTRAM_A=[FALSE:1]
  • EN_RSTRAM_B=[FALSE:1]
  • RAM_MODE=[TDP:1]
  • REGCEA=[REGCEA_INV:0] [REGCEA:1]
  • REGCEBREGCE=[REGCEBREGCE_INV:0] [REGCEBREGCE:1]
  • RSTA=[RSTA:1] [RSTA_INV:0]
  • RSTBRST=[RSTBRST:1] [RSTBRST_INV:0]
  • RSTTYPE=[SYNC:1]
  • RST_PRIORITY_A=[CE:1]
  • RST_PRIORITY_B=[CE:1]
  • WEAWEL0=[WEAWEL0:1] [WEAWEL0_INV:0]
  • WEAWEL1=[WEAWEL1_INV:0] [WEAWEL1:1]
  • WEBWEU0=[WEBWEU0:1] [WEBWEU0_INV:0]
  • WEBWEU1=[WEBWEU1:1] [WEBWEU1_INV:0]
  • WRITE_MODE_A=[WRITE_FIRST:1]
  • WRITE_MODE_B=[WRITE_FIRST:1]
 REG_SR
  • CK=[CK:230] [CK_INV:1]
  • LATCH_OR_FF=[FF:230] [LATCH:1]
  • SRINIT=[SRINIT0:202] [SRINIT1:29]
  • SYNC_ATTR=[ASYNC:87] [SYNC:144]
 SLICEL
  • CLK=[CLK:22] [CLK_INV:0]
 SLICEM
  • CLK=[CLK:28] [CLK_INV:0]
 SLICEX
  • CLK=[CLK:73] [CLK_INV:1]
 
Pin Data
BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
 BSCAN_BSCAN
  • DRCK=1
  • SEL=1
  • SHIFT=1
  • TDI=1
  • TDO=1
  • UPDATE=1
 BUFG
  • I0=2
  • O=2
 BUFG_BUFG
  • I0=2
  • O=2
 CARRY4
  • CIN=14
  • CO0=4
  • CO3=14
  • CYINIT=11
  • DI0=21
  • DI1=19
  • DI2=19
  • DI3=14
  • O0=17
  • O1=17
  • O2=15
  • O3=15
  • S0=25
  • S1=21
  • S2=19
  • S3=19
 FF_SR
  • CE=10
  • CK=27
  • D=27
  • Q=27
  • SR=23
 HARD0
  • 0=1
 HARD1
  • 1=10
 IOB
  • I=1
  • O=8
  • PAD=9
 IOB_IMUX
  • I=1
  • OUT=1
 IOB_INBUF
  • OUT=1
  • PAD=1
 IOB_OUTBUF
  • IN=8
  • OUT=8
 LUT5
  • A1=1
  • A2=7
  • A3=9
  • A4=7
  • A5=29
  • O5=93
 LUT6
  • A1=20
  • A2=27
  • A3=50
  • A4=137
  • A5=76
  • A6=139
  • O6=151
 LUT_OR_MEM5
  • A1=2
  • A2=2
  • A3=2
  • A4=2
  • A5=2
  • CLK=2
  • DI1=2
  • O5=2
  • WE=2
 LUT_OR_MEM6
  • A1=60
  • A2=60
  • A3=60
  • A4=60
  • A5=60
  • A6=60
  • CLK=60
  • DI1=29
  • DI2=31
  • MC31=49
  • O6=60
  • WE=60
 PAD
  • PAD=9
 RAMB16BWER
  • ADDRA0=2
  • ADDRA1=2
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=2
  • ADDRA3=2
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • ADDRB0=2
  • ADDRB1=2
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB2=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=2
  • CLKB=2
  • DIA0=2
  • DIA1=2
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA16=2
  • DIA17=2
  • DIA18=2
  • DIA19=2
  • DIA2=2
  • DIA20=2
  • DIA21=2
  • DIA22=2
  • DIA23=2
  • DIA24=2
  • DIA25=2
  • DIA26=2
  • DIA27=2
  • DIA28=2
  • DIA29=2
  • DIA3=2
  • DIA30=2
  • DIA31=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIB0=2
  • DIB1=2
  • DIB10=2
  • DIB11=2
  • DIB12=2
  • DIB13=2
  • DIB14=2
  • DIB15=2
  • DIB16=2
  • DIB17=2
  • DIB18=2
  • DIB19=2
  • DIB2=2
  • DIB20=2
  • DIB21=2
  • DIB22=2
  • DIB23=2
  • DIB24=2
  • DIB25=2
  • DIB26=2
  • DIB27=2
  • DIB28=2
  • DIB29=2
  • DIB3=2
  • DIB30=2
  • DIB31=2
  • DIB4=2
  • DIB5=2
  • DIB6=2
  • DIB7=2
  • DIB8=2
  • DIB9=2
  • DIPA0=2
  • DIPA1=2
  • DIPA2=2
  • DIPA3=2
  • DIPB0=2
  • DIPB1=2
  • DIPB2=2
  • DIPB3=2
  • DOA0=2
  • DOA1=2
  • DOA2=2
  • DOA3=2
  • ENA=2
  • ENB=2
  • REGCEA=2
  • REGCEB=2
  • RSTA=2
  • RSTB=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
 RAMB16BWER_RAMB16BWER
  • ADDRA0=2
  • ADDRA1=2
  • ADDRA10=2
  • ADDRA11=2
  • ADDRA12=2
  • ADDRA13=2
  • ADDRA2=2
  • ADDRA3=2
  • ADDRA4=2
  • ADDRA5=2
  • ADDRA6=2
  • ADDRA7=2
  • ADDRA8=2
  • ADDRA9=2
  • ADDRB0=2
  • ADDRB1=2
  • ADDRB10=2
  • ADDRB11=2
  • ADDRB12=2
  • ADDRB13=2
  • ADDRB2=2
  • ADDRB3=2
  • ADDRB4=2
  • ADDRB5=2
  • ADDRB6=2
  • ADDRB7=2
  • ADDRB8=2
  • ADDRB9=2
  • CLKA=2
  • CLKB=2
  • DIA0=2
  • DIA1=2
  • DIA10=2
  • DIA11=2
  • DIA12=2
  • DIA13=2
  • DIA14=2
  • DIA15=2
  • DIA16=2
  • DIA17=2
  • DIA18=2
  • DIA19=2
  • DIA2=2
  • DIA20=2
  • DIA21=2
  • DIA22=2
  • DIA23=2
  • DIA24=2
  • DIA25=2
  • DIA26=2
  • DIA27=2
  • DIA28=2
  • DIA29=2
  • DIA3=2
  • DIA30=2
  • DIA31=2
  • DIA4=2
  • DIA5=2
  • DIA6=2
  • DIA7=2
  • DIA8=2
  • DIA9=2
  • DIB0=2
  • DIB1=2
  • DIB10=2
  • DIB11=2
  • DIB12=2
  • DIB13=2
  • DIB14=2
  • DIB15=2
  • DIB16=2
  • DIB17=2
  • DIB18=2
  • DIB19=2
  • DIB2=2
  • DIB20=2
  • DIB21=2
  • DIB22=2
  • DIB23=2
  • DIB24=2
  • DIB25=2
  • DIB26=2
  • DIB27=2
  • DIB28=2
  • DIB29=2
  • DIB3=2
  • DIB30=2
  • DIB31=2
  • DIB4=2
  • DIB5=2
  • DIB6=2
  • DIB7=2
  • DIB8=2
  • DIB9=2
  • DIPA0=2
  • DIPA1=2
  • DIPA2=2
  • DIPA3=2
  • DIPB0=2
  • DIPB1=2
  • DIPB2=2
  • DIPB3=2
  • DOA0=2
  • DOA1=2
  • DOA2=2
  • DOA3=2
  • ENA=2
  • ENB=2
  • REGCEA=2
  • REGCEB=2
  • RSTA=2
  • RSTB=2
  • WEA0=2
  • WEA1=2
  • WEA2=2
  • WEA3=2
  • WEB0=2
  • WEB1=2
  • WEB2=2
  • WEB3=2
 RAMB8BWER
  • ADDRAWRADDR0=1
  • ADDRAWRADDR1=1
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR2=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR0=1
  • ADDRBRDADDR1=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR2=1
  • ADDRBRDADDR3=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOADO0=1
  • DOADO1=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
 RAMB8BWER_RAMB8BWER
  • ADDRAWRADDR0=1
  • ADDRAWRADDR1=1
  • ADDRAWRADDR10=1
  • ADDRAWRADDR11=1
  • ADDRAWRADDR12=1
  • ADDRAWRADDR2=1
  • ADDRAWRADDR3=1
  • ADDRAWRADDR4=1
  • ADDRAWRADDR5=1
  • ADDRAWRADDR6=1
  • ADDRAWRADDR7=1
  • ADDRAWRADDR8=1
  • ADDRAWRADDR9=1
  • ADDRBRDADDR0=1
  • ADDRBRDADDR1=1
  • ADDRBRDADDR10=1
  • ADDRBRDADDR11=1
  • ADDRBRDADDR12=1
  • ADDRBRDADDR2=1
  • ADDRBRDADDR3=1
  • ADDRBRDADDR4=1
  • ADDRBRDADDR5=1
  • ADDRBRDADDR6=1
  • ADDRBRDADDR7=1
  • ADDRBRDADDR8=1
  • ADDRBRDADDR9=1
  • CLKAWRCLK=1
  • CLKBRDCLK=1
  • DIADI0=1
  • DIADI1=1
  • DIADI10=1
  • DIADI11=1
  • DIADI12=1
  • DIADI13=1
  • DIADI14=1
  • DIADI15=1
  • DIADI2=1
  • DIADI3=1
  • DIADI4=1
  • DIADI5=1
  • DIADI6=1
  • DIADI7=1
  • DIADI8=1
  • DIADI9=1
  • DIBDI0=1
  • DIBDI1=1
  • DIBDI10=1
  • DIBDI11=1
  • DIBDI12=1
  • DIBDI13=1
  • DIBDI14=1
  • DIBDI15=1
  • DIBDI2=1
  • DIBDI3=1
  • DIBDI4=1
  • DIBDI5=1
  • DIBDI6=1
  • DIBDI7=1
  • DIBDI8=1
  • DIBDI9=1
  • DIPADIP0=1
  • DIPADIP1=1
  • DIPBDIP0=1
  • DIPBDIP1=1
  • DOADO0=1
  • DOADO1=1
  • ENAWREN=1
  • ENBRDEN=1
  • REGCEA=1
  • REGCEBREGCE=1
  • RSTA=1
  • RSTBRST=1
  • WEAWEL0=1
  • WEAWEL1=1
  • WEBWEU0=1
  • WEBWEU1=1
 REG_SR
  • CE=84
  • CK=231
  • D=231
  • Q=231
  • SR=177
 SELMUX2_1
  • 0=12
  • 1=12
  • OUT=12
  • S0=12
 SLICEL
  • A=1
  • A2=1
  • A3=1
  • A4=18
  • A5=1
  • A6=18
  • AMUX=1
  • AQ=21
  • B=1
  • B4=18
  • B5=1
  • B6=16
  • BQ=18
  • C1=3
  • C2=3
  • C3=3
  • C4=18
  • C5=3
  • C6=18
  • CE=13
  • CIN=14
  • CLK=22
  • CMUX=3
  • COUT=10
  • CQ=15
  • CX=3
  • D1=2
  • D2=3
  • D3=3
  • D4=18
  • D5=3
  • D6=13
  • DQ=15
  • SR=20
 SLICEM
  • A=16
  • A1=27
  • A2=27
  • A3=27
  • A4=27
  • A5=27
  • A6=27
  • AI=18
  • AMUX=4
  • AQ=2
  • AX=10
  • B=1
  • B1=12
  • B2=12
  • B3=12
  • B4=12
  • B5=12
  • B6=12
  • BI=2
  • BMUX=2
  • BQ=2
  • BX=8
  • C=2
  • C1=11
  • C2=11
  • C3=11
  • C4=11
  • C5=11
  • C6=10
  • CE=28
  • CI=3
  • CLK=28
  • CMUX=1
  • COUT=4
  • CQ=2
  • CX=6
  • D=3
  • D1=11
  • D2=11
  • D3=11
  • D4=11
  • D5=11
  • D6=11
  • DI=8
  • DMUX=24
  • DQ=2
  • DX=7
 SLICEX
  • A=17
  • A1=7
  • A2=9
  • A3=14
  • A4=21
  • A5=27
  • A6=24
  • AMUX=10
  • AQ=60
  • AX=52
  • B=10
  • B1=5
  • B2=6
  • B3=12
  • B4=15
  • B5=21
  • B6=15
  • BMUX=9
  • BQ=35
  • BX=28
  • C=14
  • C1=3
  • C2=7
  • C3=10
  • C4=15
  • C5=23
  • C6=18
  • CE=16
  • CLK=74
  • CMUX=10
  • CQ=26
  • CX=22
  • D=13
  • D1=1
  • D2=2
  • D3=12
  • D4=16
  • D5=20
  • D6=17
  • DMUX=6
  • DQ=33
  • DX=28
  • SR=56
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc6slx9-tqg144-2 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc6slx9-tqg144-2 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off -pr off -lc off -power off -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -mt off <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 2 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_compxlibgui 1 1 0 0 0 0 0
_impact 4 3 0 0 0 0 0
bitgen 13 13 0 0 0 0 0
bitinit 1 1 0 0 0 0 0
cse_server 1 0 0 0 0 0 0
edif2ngd 4 4 0 0 0 0 0
elfcheck 101 101 0 0 0 0 0
libgen 9 9 0 0 0 0 0
map 17 15 0 0 0 0 0
netgen 4 4 0 0 0 0 0
ngc2edif 8 8 0 0 0 0 0
ngcbuild 36 36 0 0 0 0 0
ngdbuild 17 17 0 0 0 0 0
obngc 3 3 0 0 0 0 0
par 15 15 0 0 0 0 0
partgen 29 27 0 0 0 0 0
platgen 8 8 0 0 0 0 0
psf2Edward 7 7 0 0 0 0 0
trce 14 14 0 0 0 0 0
xps 15 14 0 0 0 0 0
xpwr 2 2 0 0 0 0 0
xst 91 91 0 0 0 0 0
 
Help Statistics
Help files
/doc/usenglish/isehelp/cgn_c_overview.htm ( 2 )
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2011-12-12T15:10:21
PROP_intWbtProjectID=6722449814024B449CE8FDE2FE8F11EF PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_AutoTop=true
PROP_DevFamily=Spartan6 PROP_DevDevice=xc6slx9
PROP_DevFamilyPMName=spartan6 PROP_DevPackage=tqg144
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-2
PROP_PreferredLanguage=Verilog FILE_CDC=1
FILE_UCF=1 FILE_VERILOG=1
 
Core Statistics
Core Type=chipscope_icon_v1_05_a
c_build_revision=0 c_core_major_ver=1 c_core_minor_alpha_ver=97 c_core_minor_ver=5
c_core_type=1 c_example_design=false c_major_version=13 c_mfg_id=1
c_minor_version=2 c_num_control_ports=1 c_part_idcode_register=0 c_use_bufr=0
c_use_control0=1 c_use_control1=0 c_use_control10=0 c_use_control11=0
c_use_control12=0 c_use_control13=0 c_use_control14=0 c_use_control2=0
c_use_control3=0 c_use_control4=0 c_use_control5=0 c_use_control6=0
c_use_control7=0 c_use_control8=0 c_use_control9=0 c_use_ext_bscan=0
c_use_jtag_bufg=1 c_use_new_parser=0 c_use_sim=0 c_use_softbscan=0
c_use_unused_bscan=0 c_use_xst_tck_workaround=1 c_user_scan_chain=1 c_xco_list=Number_Control_Ports=1;Use_Ext_Bscan=false;User_Scan_Chain=USER1;Enable_Jtag_Bufg=true;Use_Unused_Bscan=false;Use_Softbscan=false
c_xdevicefamily=spartan6
Core Type=chipscope_ila_v1_04_a
c_build_revision=0 c_core_major_ver=1 c_core_minor_alpha_ver=97 c_core_minor_ver=4
c_core_type=2 c_data_depth=4096 c_data_width=1 c_example_design=false
c_ext_cap_pin_mode=0 c_ext_cap_rate_mode=0 c_ext_cap_use_reg=1 c_m0_tpid=0
c_m0_type=1 c_m10_tpid=10 c_m10_type=0 c_m11_tpid=11
c_m11_type=0 c_m12_tpid=12 c_m12_type=0 c_m13_tpid=13
c_m13_type=0 c_m14_tpid=14 c_m14_type=0 c_m15_tpid=15
c_m15_type=0 c_m1_tpid=1 c_m1_type=0 c_m2_tpid=2
c_m2_type=0 c_m3_tpid=3 c_m3_type=0 c_m4_tpid=4
c_m4_type=0 c_m5_tpid=5 c_m5_type=0 c_m6_tpid=6
c_m6_type=0 c_m7_tpid=7 c_m7_type=0 c_m8_tpid=8
c_m8_type=0 c_m9_tpid=9 c_m9_type=0 c_major_version=13
c_mcnt0_width=1 c_mcnt10_width=1 c_mcnt11_width=1 c_mcnt12_width=1
c_mcnt13_width=1 c_mcnt14_width=1 c_mcnt15_width=1 c_mcnt1_width=1
c_mcnt2_width=1 c_mcnt3_width=1 c_mcnt4_width=1 c_mcnt5_width=1
c_mcnt6_width=1 c_mcnt7_width=1 c_mcnt8_width=1 c_mcnt9_width=1
c_mfg_id=1 c_minor_version=2 c_num_ext_cap_pins=8 c_num_match_units=1
c_num_tseq_cnt=0 c_num_tseq_states=16 c_ram_type=1 c_srl16_type=2
c_tc_mcnt_width=1 c_timestamp_depth=512 c_timestamp_type=0 c_timestamp_width=32
c_trig0_width=8 c_trig10_width=1 c_trig11_width=1 c_trig12_width=1
c_trig13_width=1 c_trig14_width=1 c_trig15_width=1 c_trig1_width=1
c_trig2_width=1 c_trig3_width=1 c_trig4_width=1 c_trig5_width=1
c_trig6_width=1 c_trig7_width=1 c_trig8_width=1 c_trig9_width=1
c_tseq_cnt0_width=1 c_tseq_cnt1_width=1 c_tseq_type=1 c_use_atc_clkin=0
c_use_data=0 c_use_gap=0 c_use_inv_clk=0 c_use_mcnt0=0
c_use_mcnt1=0 c_use_mcnt10=0 c_use_mcnt11=0 c_use_mcnt12=0
c_use_mcnt13=0 c_use_mcnt14=0 c_use_mcnt15=0 c_use_mcnt2=0
c_use_mcnt3=0 c_use_mcnt4=0 c_use_mcnt5=0 c_use_mcnt6=0
c_use_mcnt7=0 c_use_mcnt8=0 c_use_mcnt9=0 c_use_rpm=1
c_use_storage_qual=1 c_use_tc_mcnt=0 c_use_trig0=1 c_use_trig1=0
c_use_trig10=0 c_use_trig11=0 c_use_trig12=0 c_use_trig13=0
c_use_trig14=0 c_use_trig15=0 c_use_trig2=0 c_use_trig3=0
c_use_trig4=0 c_use_trig5=0 c_use_trig6=0 c_use_trig7=0
c_use_trig8=0 c_use_trig9=0 c_use_trig_out=0 c_use_trigdata0=1
c_use_trigdata1=0 c_use_trigdata10=0 c_use_trigdata11=0 c_use_trigdata12=0
c_use_trigdata13=0 c_use_trigdata14=0 c_use_trigdata15=0 c_use_trigdata2=0
c_use_trigdata3=0 c_use_trigdata4=0 c_use_trigdata5=0 c_use_trigdata6=0
c_use_trigdata7=0 c_use_trigdata8=0 c_use_trigdata9=0 c_xco_list=Component_Name=ila_pro_0;Number_Of_Trigger_Ports=1;Max_Sequence_Levels=16;Use_RPMs=true;Enable_Trigger_Output_Port=false;Sample_On=Rising;Sample_Data_Depth=4096;Enable_Storage_Qualification=true;Data_Same_As_Trigger=true;Data_Port_Width=0;Trigger_Port_Width_1=8;Match_Units_1=1;Counter_Width_1=Disabled;Match_Type_1=basic_with_edges;Exclude_From_Data_Storage_1=false;Trigger_Port_Width_2=1;Match_Units_2=1;Counter_Width_2=Disabled;Match_Type_2=basic;Exclude_From_Data_Storage_2=false;Trigger_Port_Width_3=1;Match_Units_3=1;Counter_Width_3=Disabled;Match_Type_3=basic;Exclude_From_Data_Storage_3=false;Trigger_Port_Width_4=1;Match_Units_4=1;Counter_Width_4=Disabled;Match_Type_4=basic;Exclude_From_Data_Storage_4=false;Trigger_Port_Width_5=1;Match_Units_5=1;Counter_Width_5=Disabled;Match_Type_5=basic;Exclude_From_Data_Storage_5=false;Trigger_Port_Width_6=1;Match_Units_6=1;Counter_Width_6=Disabled;Match_Type_6=basic;Exclude_From_Data_Storage_6=false;Trigger_Port_Width_7=1;Match_Units_7=1;Counter_Width_7=Disabled;Match_Type_7=basic;Exclude_From_Data_Storage_7=false;Trigger_Port_Width_8=1;Match_Units_8=1;Counter_Width_8=Disabled;Match_Type_8=basic;Exclude_From_Data_Storage_8=false;Trigger_Port_Width_9=1;Match_Units_9=1;Counter_Width_9=Disabled;Match_Type_9=basic;Exclude_From_Data_Storage_9=false;Trigger_Port_Width_10=1;Match_Units_10=1;Counter_Width_10=Disabled;Match_Type_10=basic;Exclude_From_Data_Storage_10=false;Trigger_Port_Width_11=1;Match_Units_11=1;Counter_Width_11=Disabled;Match_Type_11=basic;Exclude_From_Data_Storage_11=false;Trigger_Port_Width_12=1;Match_Units_12=1;Counter_Width_12=Disabled;Match_Type_12=basic;Exclude_From_Data_Storage_12=false;Trigger_Port_Width_13=1;Match_Units_13=1;Counter_Width_13=Disabled;Match_Type_13=basic;Exclude_From_Data_Storage_13=false;Trigger_Port_Width_14=1;Match_Units_14=1;Counter_Width_14=Disabled;Match_Type_14=basic;Exclude_From_Data_Storage_14=false;Trigger_Port_Width_15=1;Match_Units_15=1;Counter_Width_15=Disabled;Match_Type_15=basic;Exclude_From_Data_Storage_15=false;Trigger_Port_Width_16=1;Match_Units_16=1;Counter_Width_16=Disabled;Match_Type_16=basic;Exclude_From_Data_Storage_16=false
c_xdevicefamily=spartan6
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN6=1 NGDBUILD_NUM_BUFG=1 NGDBUILD_NUM_BUFGP=1 NGDBUILD_NUM_FD=25
NGDBUILD_NUM_FDC=9 NGDBUILD_NUM_FDCE=16 NGDBUILD_NUM_FDE=32 NGDBUILD_NUM_FDP=18
NGDBUILD_NUM_FDR=69 NGDBUILD_NUM_FDRE=78 NGDBUILD_NUM_FDS=10 NGDBUILD_NUM_GND=7
NGDBUILD_NUM_INV=7 NGDBUILD_NUM_LDC=1 NGDBUILD_NUM_LUT1=64 NGDBUILD_NUM_LUT2=26
NGDBUILD_NUM_LUT3=20 NGDBUILD_NUM_LUT4=87 NGDBUILD_NUM_LUT5=1 NGDBUILD_NUM_LUT6=24
NGDBUILD_NUM_MUXCY=7 NGDBUILD_NUM_MUXCY_L=70 NGDBUILD_NUM_MUXF7=10 NGDBUILD_NUM_MUXF8=2
NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_RAMB16BWER=2 NGDBUILD_NUM_RAMB8BWER=1 NGDBUILD_NUM_SRL16=8
NGDBUILD_NUM_SRL16E=1 NGDBUILD_NUM_SRLC16E=24 NGDBUILD_NUM_SRLC32E=29 NGDBUILD_NUM_VCC=10
NGDBUILD_NUM_XORCY=64
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_BSCAN_SPARTAN6=1 NGDBUILD_NUM_BUFG=2 NGDBUILD_NUM_FD=25 NGDBUILD_NUM_FDC=9
NGDBUILD_NUM_FDCE=16 NGDBUILD_NUM_FDE=32 NGDBUILD_NUM_FDP=18 NGDBUILD_NUM_FDR=69
NGDBUILD_NUM_FDRE=78 NGDBUILD_NUM_FDS=10 NGDBUILD_NUM_GND=7 NGDBUILD_NUM_IBUFG=1
NGDBUILD_NUM_INV=7 NGDBUILD_NUM_LDC=1 NGDBUILD_NUM_LUT1=64 NGDBUILD_NUM_LUT2=26
NGDBUILD_NUM_LUT3=20 NGDBUILD_NUM_LUT4=87 NGDBUILD_NUM_LUT5=1 NGDBUILD_NUM_LUT6=24
NGDBUILD_NUM_MUXCY=7 NGDBUILD_NUM_MUXCY_L=70 NGDBUILD_NUM_MUXF7=10 NGDBUILD_NUM_MUXF8=2
NGDBUILD_NUM_OBUF=8 NGDBUILD_NUM_RAMB16BWER=2 NGDBUILD_NUM_RAMB8BWER=1 NGDBUILD_NUM_SRL16E=9
NGDBUILD_NUM_SRLC16E=24 NGDBUILD_NUM_SRLC32E=29 NGDBUILD_NUM_TIMESPEC=1 NGDBUILD_NUM_TS_TIMESPEC=1
NGDBUILD_NUM_VCC=10 NGDBUILD_NUM_XORCY=64
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc6slx9-2-tqg144 -top=<design_top> -opt_mode=Speed -opt_level=1
-power=NO -iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized
-rtlview=Yes -glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO
-cross_clock_analysis=NO -bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100
-dsp_utilization_ratio=100 -reduce_control_sets=Auto -fsm_extract=YES -fsm_encoding=Auto
-safe_implementation=No -fsm_style=LUT -ram_extract=Yes -ram_style=Auto
-rom_extract=Yes -shreg_extract=YES -rom_style=Auto -auto_bram_packing=NO
-resource_sharing=YES -async_to_sync=NO -use_dsp48=Auto -iobuf=YES
-max_fanout=100000 -bufg=16 -register_duplication=YES -register_balancing=No
-optimize_primitives=NO -use_clock_enable=Auto -use_sync_set=Auto -use_sync_reset=Auto
-iob=Auto -equivalent_register_removal=YES -slice_utilization_ratio_maxmargin=5