# 
# Synthesis run script generated by Vivado
# 

create_project -in_memory -part xc7k325tffg900-2

set_param project.singleFileAddWarning.threshold 0
set_param project.compositeFile.enableAutoGeneration 0
set_param synth.vivado.isSynthRun true
set_property webtalk.parent_dir E:/workspace/KXK7T_PCIE/Product_CD/KXK7T_PCIE/FPGA_RefDesign/LED_Switch/vivado/LED_Switch.cache/wt [current_project]
set_property parent.project_path E:/workspace/KXK7T_PCIE/Product_CD/KXK7T_PCIE/FPGA_RefDesign/LED_Switch/vivado/LED_Switch.xpr [current_project]
set_property default_lib xil_defaultlib [current_project]
set_property target_language Verilog [current_project]
set_property ip_output_repo e:/workspace/KXK7T_PCIE/Product_CD/KXK7T_PCIE/FPGA_RefDesign/LED_Switch/vivado/LED_Switch.cache/ip [current_project]
set_property ip_cache_permissions {read write} [current_project]
read_vhdl -library xil_defaultlib E:/workspace/KXK7T_PCIE/Product_CD/KXK7T_PCIE/FPGA_RefDesign/LED_Switch/src/LED_Switch.vhd
# Mark all dcp files as not used in implementation to prevent them from being
# stitched into the results of this synthesis run. Any black boxes in the
# design are intentionally left as such for best results. Dcp files will be
# stitched into the design at a later time, either when this synthesis run is
# opened, or when it is stitched into a dependent implementation run.
foreach dcp [get_files -quiet -all -filter file_type=="Design\ Checkpoint"] {
  set_property used_in_implementation false $dcp
}
read_xdc E:/workspace/KXK7T_PCIE/Product_CD/KXK7T_PCIE/FPGA_RefDesign/LED_Switch/src/LED_Switch.xdc
set_property used_in_implementation false [get_files E:/workspace/KXK7T_PCIE/Product_CD/KXK7T_PCIE/FPGA_RefDesign/LED_Switch/src/LED_Switch.xdc]


synth_design -top LED_Switch -part xc7k325tffg900-2


write_checkpoint -force -noxdef LED_Switch.dcp

catch { report_utilization -file LED_Switch_utilization_synth.rpt -pb LED_Switch_utilization_synth.pb }
