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PMOS对管实现耐高逆向电压的高端理想二极管设计
集成电路应用
徐启永,陈石平
广东科贸职业学院
摘要: 针对电流倒灌问题,提出了PMOS主管与PNP对管的电路改进设计方案。该电路主要由PMOS主管、比较器电路以及保护电路等部分组成。比较器电路的作用在于对比输入端电源VCC与输出端电源Vout的数值大小,其输出的比较信号连接至PMOS主管的栅极,以此控制PMOS主管的导通与截止状态。保护电路借助二极管较高的反向击穿电压以及单向导通特性,采用电阻分压、稳压二极管等分压电路,设计出三种高端理想二极管电路,并针对分压电阻的取值范围进行理论推导以及软件仿真验证。研究结果显示,所设计的三种电路具备防止电流倒灌、耐受高反向电压等功能,能够对前级电路起到保护作用,且具有电路结构简单、成本低的优势。
中图分类号:TN710.2文献标识码:ADOI:10.19339/j.issn.1674-2583.2026.03.003
中文引用格式:徐启永,陈石平. PMOS对管实现耐高逆向电压的高端理想二极管设计[J].集成电路应用,2026,43(3):10-14.
英文引用格式:Xu Qiyong, Chen Shiping. Highside ideal diode with high reverse voltage capability using PMOS transistor pair [J].Application of IC,2026,43(3):10-14.
High-side ideal diode with high reverse voltage capability using PMOS transistor pair
Xu Qiyong, Chen Shiping
Guangdong Polytechnic of Science and Trade
Abstract: A circuit design scheme featuring a PMOS main transistor and a PNP pair is proposed to address the issue of current backflow.The circuit primarily consists of a PMOS main transistor, a comparator circuit, and a protection circuit. The comparator compares the input power supply VCC with the output power supply Vout, and its output signal is connected to the gate of the PMOS main transistor to control its switching state. Leveraging the high reverse breakdown voltage and unidirectional conduction characteristics of diodes, the protection circuit employs resistor voltage division and Zener diode voltage division circuits to design three high-side ideal diode circuits. Theoretical derivations and software simulations are performed to determine the range of voltage-divider resistor values. The results demonstrate that the three designed circuits can prevent reverse current flow, withstand high reverse voltages, and protect the preceding circuitry, while also featuring simple structures and low cost.
Key words : high-side ideal diode;Zener diode; reverse breakdown voltage; transistor pair

引言

二极管由于具有单向导通特性,耐反向电压较高,反向电流较小,具有较强的防止倒灌功能[1-2];肖特基二极管串连在电源输出端上具有较小压降,耐反向电压比较低,反向漏电流较大,防止倒灌功能较弱;使用MOS主管作为理想二极管的导通压降比较小,具有低阻抗特性和一定的耐反向电压。

高端理想二极管[3]实现的方案包括:采用“PMOS主管+PMOS对管”[4-5],但这种方案控制逻辑复杂、成本较高、存在误导通风险。“PMOS主管+PNP对管”技术方案[6]可实现低导通压降、具备自动极性识别能力、电路结构简洁可靠,且无需额外电源即可完成高边驱动,但当电路中的栅极驱动电压或电流不足时易引起误判风险。因此本研究在此基础上增加了比较器电路以及保护电路等。


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作者信息:

徐启永,陈石平

(广东科贸职业学院,广东广州510430)

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