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基于Innovus的复杂时钟结构分析及实现
2020年电子技术应用第8期
曾晋伟
深圳市中兴微电子技术有限公司,四川 成都610041
摘要: 在先进工艺节点下,随着设计规模越来越大,时钟频率越来越高以及时钟结构越来越复杂,最终整个设计收敛对于时钟质量的依赖越来越明显。针对类似多输入动态mux复杂时钟、IP模块多内部输出时钟等复杂的时钟结构,采用分析时钟框图及基于Innovus工具从网表中提取时钟结构的分析方式进行时钟结构上的详细梳理,提出针对时钟结构分析及clock spec的优化方法。同时在一个超大规模的16 nm top design上基于优化后的clock spec进行CTS,并结合multi-tap的clock tree做法,从得到的结果可以发现在run time、clock latency等方面都有较大的提升,能够满足项目要求的时钟长度等要求,有效避免block接口的时序冲突。
中图分类号: TN402
文献标识码: A
DOI:10.16157/j.issn.0258-7998.209803
中文引用格式: 曾晋伟. 基于Innovus的复杂时钟结构分析及实现[J].电子技术应用,2020,46(8):64-67.
英文引用格式: Zeng Jinwei. Complicated clock structure analysis and implementation with Innovus implementation system[J]. Application of Electronic Technique,2020,46(8):64-67.
Complicated clock structure analysis and implementation with Innovus implementation system
Zeng Jinwei
Sanechips Technology Co.,Ltd.,Chengdu 610041,China
Abstract: In advanced process node, as the design scale becomes larger and larger, the clock frequency becomes higher and the clock structure becomes more and more complicated, it is increasingly found that the closure of the design depends more and more on the clock quality. For complicated clock structures such as multi-input dynamic mux, IP modules with multiple internal output clocks, etc., the clock structure is analyzed, and the clock structure is extracted from the netlist based on the Innovus tool, clock spec will be updated based on these analysis. At the same time, CTS is performed on an ultra-large 16 nm top design based on the optimized clock spec, combined with the multi-tap clock tree methodology. From the results obtained, it can be found that the run time, clock latency and other aspects have been greatly improved. It can meet the requirements such as the clock length required by the project, and effectively avoid the timing conflict of the block interface.
Key words : Innovus;physical design;clock tree;multi-tap CTS

0 引言

    随着集成电路工艺进入先进节点(Advanced Node),以及应用场景的不断增加,带来芯片设计规模越来越大以及时钟结构更加复杂,针对时钟结构的分析与时钟的实现也更加困难。就时钟树综合(Clock Tree Synthesis,CTS)而言,时钟结构复杂程度的增加,可能会带来公共路径(Common Path)的长度减少,片上误差(On Chip Variation,OCV)的影响增加,CTS迭代时间(Turn-Around Time)增加,以及时钟上功耗增加等问题。因此,在物理实现中,CTS变得越来越重要。

    在本文中,借助于Cadence公司的自动化布局布线工具Innovus,首先探讨了针对复杂时钟结构的时钟如何进行分析,其次基于分析结果提出时钟实现上可能出现的问题以及解决方案,再次,基于调整进行CTS实现,并与传统CTS方案的结果进行对比,最后对本文进行总结并对结论进行进一步分析。




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作者信息:

曾晋伟

(深圳市中兴微电子技术有限公司,四川 成都610041)

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