中图分类号：TN43文献标识码：ADOI:10.19339/j.issn.1674-2583.2026.03.002
中文引用格式：杨琨，张洪俞. 控制LDO压降状态静态功耗的电路设计［J］.集成电路应用，2026，43（3）：5-9.
英文引用格式：Yang Kun，Zhang Hongyu. Circuit design for controlling static power consumption of LDO in dropout state［J］.Application of IC，2026，43（3）：5-9.

Circuit design for controlling static power consumption of LDO in dropout state

Abstract： To address the problem of static power consumption sharply increasing in traditional low-dropout linear regulators (LDO) under voltage drop conditions, a low-power LDO circuit based on an auxiliary current mirror branch is proposed. By introducing an auxiliary branch,which is composed of a P-type MOS transistor M3, a diode-connected P-type MOS transistor M4, and a nA-level self-bias current source, into the traditional LDO, and using the SP signal line to control the gate voltage of M3, the current growth of the second stage of the operational amplifier under voltage drop conditions is effectively limited. Simulation results based on a 0.18 μm CMOS process show that under a deep voltage drop condition of VIN = 1.0 V, the static current is only 1.0 μA, which is about 755 times lower than the traditional structure; in normal conditions, the static current is 485 nA. The study further conducted robustness verification across five process corners, the full temperature range, and 5 000 Monte Carlo simulations. An nA-level self-bias current source and a zero-static-power startup circuit are designed, establishing a “power—load—area” performance trade-off model.

Key words : LDO; static power consumption; dropout state; current mirror; nA-level bias current source