Σ-Δ转换器使用从调节器得到的许多采样值产生1bit码流。Σ-ΔADC以高采样速率使用输入信号量化器完成这个任务。像所有的量化器一样，Σ-ΔADC调节器获取输入，产生数字码流表征输入电压。可以观察时域或频域的Σ-Δ调节器。如果看时域表现，可以见一阶调节器的结构(图1)。

　　调节器测量模拟输入信号和反馈DAC的模拟输出。随后一个积分器测量求和节点的模拟电压输出，为1位ADC呈现出一个斜坡信号。1位ADC转换积分器输出信号为数字一或零。使用系统时钟，ADC将1位数字信号送到调节器输出，也通过反馈回输入，在这里1位DAC为等待。

　　1位ADC将信号量化为离散的输出编码，带有转换器的量化噪声(ei)。调节器输出等于输入信号加上量化噪声(ei–ei–1)。如这个公式所示，量化噪声为调节器当前误差(ei)减去前一个误差(ei–1)的微分。时域输出信号为以采样频率FS的输入信号脉冲波形。如果将输出脉冲序列平均，它等于输入的信号值。

　　频域图反映了不同的问题（图2）。时域输出脉冲在频域内表现为输入信号（或毛刺）和变形的噪声。图2的噪声特性是调节器频率作用的关键。

　　不像大

多数量化器，Σ-Δ调节器包括形成量化噪声的积分器。调节器输出的噪声频谱并不平滑。更重要的，在频率分析中，可以看到积分器怎样在更高频率处形成噪声，便于产生更高分辨率的结果。

　　图2中调节器输出显示了调节器的量化噪声在0Hz时开始为低电平，快速上升，然后在调节器采样频率为最大值处稳定。

　　二阶调节器进行两次积分，而不是仅有一次，是最小化低频率量化噪声的一种好方法。大多数Σ-Δ调节器具有更高的阶数。例如，更常用的Σ-Δ转换器的设计包括二、三、四、五或六阶调节器。多阶调节器在更高频率形成更大的量化噪声。

　　英文原文：

　　Delta-sigma ADCs in a nutshell, part 2: the modulator

　　Unlike most quantizers, the delta-sigma modulator includes an integrator that shapes the quantization noise.

　　By Bonnie Baker -- EDN, 1/17/2008

　　A delta-sigma converter uses many samples from the modulator to produce a stream of 1-bit codes. The delta-sigma ADC accomplishes this task by using an input-signal quantizer running at a high sample rate. Like all quantizers, the delta-sigma modulator takes an input and produces a stream of digital values that represents the voltage of the input. You can look at the delta-sigma modulator in the time or in the frequency domain. If you look at a time-domain representation, you can see the mechanics of a first-order modulator (Figure 1).

　　The modulator measures the difference between the analog-input signal and the analog output of a feedback DAC. An integrator then measures the analog-voltage output of the summing junction and presents a sloping signal to the 1-bit ADC. The 1-bit ADC converts the integrator’s output signal to a digital one or zero. Using the system clock, the ADC sends the 1-bit digital signal to the modulator’s output, as well as back through the feedback loop, where a 1-bit DAC is waiting.

　　The 1-bit ADC digitizes the signal to a coarse output code that has the quantization noise (ei) of the converter. The modulator output is equal to the input plus the quantization noise, (ei–ei–1). As this formula shows, the quantization noise is the difference of the current error (ei) minus the previous error (ei–1) of the modulator. The time-domain output signal is a pulse-wave representation of the input signal at the sampling frequency, fS. If you average the output-pulse train, it equals t

he value of the input signal.

　　The frequency-domain diagram tells a different story (Figure 2). The time-domain output pulses in the frequency domain appear as the input signal (or spur) and shaped noise. The noise characteristic in Figure 2 is the key to the modulator’s frequency operation.

　　Unlike most quantizers, the delta-sigma modulator includes an integrator that shapes the quantization noise. The noise spectrum at the modulator output is not flat. More important, in a frequency analysis, you can see how the modulator shapes the noise to higher frequencies, facilitating the production of a higher resolution result.

　　The modulator output in Figure 2 shows that the quantization noise of the modulator starts low at 0 Hz, rises rapidly, and then levels off at a maximum value at the modulator sampling frequency.

　　Integrating twice with a second-order modulator, instead of just once, is a great way to minimize low-frequency quantization noise. Most delta-sigma modulators are of a higher order. For instance, the designs of the more popular delta-sigma converters include second-, third-, fourth-, fifth, or sixth-order modulators. Multi-order modulators shape the quantization noise even harder to higher frequencies.

　　References

　　Baker, Bonnie, “Delta-sigma ADCs in a nutshell,” EDN, Dec 14, 2007, pg 22.

　　Baker, RJ, CMOS mixed-signal circuit design, Wiley & Sons, ISBN 0471227544, May 2002.