// SFR_FSM.v
module SFR_FSM (clk, Resetn, sfr4" title="sfr4">sfr4, sfr7, CPUDOUT, CPUWAITn" title="CPUWAITn">CPUWAITn, latch_RD, CPUWRn,
                CPURDn , CPUMEM);

input clk;
input [2:0] sfr4; // SFR4 Control Reg" title="Reg">Register bit 2 to 0.
input CPUWAITn; //input from Core1553
input Resetn; //global power on reset
input [15:0] CPUDOUT; // Read data input from Core1553B
output [7:0] sfr7; // SFR7 Status Regsiter
output [1:0] CPUWRn; //Output to Core1553
output CPURDn; //Output to Core1553
output [15:0] latch_RD; //read data output to Core8051
output CPUMEM; //Output to Core1553

parameter idle = 2'b0" title="b0">b00, write = 2'b01, read = 2'b10;

reg CPURDn_int, CPUMEM;
reg [1:0] CPUWRn;
reg [7:0] sfr7;
reg [15:0] latch_RD;

reg [1:0] present_st" title="present_st">present_st, next_st;

//FSM state transition
always @ (posedge clk or negedge Resetn)
begin
if (Resetn == 1'b0)
  present_st <= idle;
else
  present_st <= next_st; 
end

//FSM state definition状态机
always @ (present_st, sfr4, CPUWAITn)
begin
case (present_st)
   idle: case (sfr4)
         3'b000: next_st<= idle;
         3'b011: next_st<= write;
         3'b101: next_st<= read;
         default: next_st<= idle;
         endcase
   write: case (CPUWAITn)
          1'b0: next_st<= write;
          1'b1: next_st<= idle;
          endcase
   read: case (CPUWAITn)
         1'b0: next_st<= read;
         1'b1: next_st<= idle;
         endcase
 
   default: next_st <= idle;
endcase
end

//Output definition 输出定义
always @ (present_st)
begin
case (present_st)
idle: begin
      sfr7 <= 8'b0;
      CPUWRn <= 2'b11;
      CPURDn_int <= 1'b1;
      CPUMEM <= 1'b0;
   end
write: begin
           sfr7 <= 8'b00000001;
           CPUWRn <= 2'b00;
           CPURDn_int <= 1'b1;
           CPUMEM <= 1'b1;
     end
read:  begin
           sfr7 <= 8'b00000001;
           CPUWRn <= 2'b11;
           CPURDn_int <= 1'b0;
           CPUMEM <= 1'b1;
     end
default: begin
      sfr7 <= 8'b00000000;
      CPUWRn <= 2'b11;
      CPURDn_int <= 1'b1;
      CPUMEM <= 1'b0;
   end
endcase
end

//Latching the read data from Core1553 to Core8051
always @ (posedge clk)posedge CPURDn_int)
begin
if (CPURD_int == 1'b0)
   latch_RD <= CPUDOUT;
end

assign CPURDn = CPURDn_int;

endmodule

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http://www.actel.com/techdocs/appnotes/proasic3.aspx