《电子技术应用》
您所在的位置:首页 > 模拟设计 > 设计应用 > 基于PCIe Gen5的低成本Coupon设计
基于PCIe Gen5的低成本Coupon设计
2022年电子技术应用第6期
刘 涛,宗艳艳,王乾辉,秦玉倩,田民政,余华国
浪潮电子信息产业股份有限公司,山东 济南250101
摘要: 数字技术发展日新月异,新一代服务器产品中,PCIe Gen5信号速率已经达到32 Gb/s,为了确保其信号完整性设计,单板损耗监控必不可少,优良的Coupon设计因此显得尤为重要。传统Coupon多采用Litek探头技术,以折线方式布线,尽管技术成熟,但存在占用空间大,数据稳定性差等问题。从产品设计的低成本需求出发,对PCIe Gen5信号的低成本Coupon设计展开研究,结合差分绕线理论分析以及仿真数据,对几种不同绕线方式进行分析对比,选择了一种低空间占有率且高可靠性的Coupon布线方式,并对测试治具进行了改进。实验结果表明,提出的Coupon设计方法不仅比传统方法占用空间少,而且数据稳定性更高,更加有利于Coupon的低成本、高可靠性设计。
中图分类号: TN402
文献标识码: A
DOI:10.16157/j.issn.0258-7998.211960
中文引用格式: 刘涛,宗艳艳,王乾辉,等. 基于PCIe Gen5的低成本Coupon设计[J].电子技术应用,2022,48(6):116-120.
英文引用格式: Liu Tao,Zong Yanyan,Wang Qianhui,et al. Low-cost Coupon design based on PCIe Gen5 signal[J]. Application of Electronic Technique,2022,48(6):116-120.
Low-cost Coupon design based on PCIe Gen5 signal
Liu Tao,Zong Yanyan,Wang Qianhui,Qin Yuqian,Tian Minzheng,Yu Huaguo
Inspur Electronic Information Industry Co.,Ltd.,Jinan 250101,China
Abstract: The development of digital technology is changing rapidly. In the new generation of server products, the PCIe Gen5 signal rate has reached 32 Gb/s. In order to ensure its signal integrity design, single-board loss monitoring is essential, and a good Coupon design is therefore particularly important. Traditional Coupons mostly use Litek probe technology, and wiring in a broken line. Although the technology is mature, there are still many problems such as large space occupation and poor data stability. Based on the low-cost requirements of product design, this paper researches on the low-cost Coupon design of PCIe Gen5 signal. Different wiring methods are analyzed and compared through theoretical analysis and simulation. Then the high-reliability Coupon wiring method is selected which can also takes up less space. The test fixture is also optimized which can also improve data stability. Experimental results show that the Coupon design method proposed in this paper not only takes up less space than traditional methods, but also has higher data stability. Therefore, this method is more conducive to the low-cost and high-reliability design of Coupons.
Key words : PCIe;32 Gb/s;Coupon;phase difference;test verification

0 引言

    互联网技术飞速发展,万物高速互连早已成为不可逆转的发展趋势,为了满足日益增长的数据存储、传输与交换需求,信号速率也正在以前所未有的速度进行升级换代,以服务器系统中代表性的PCIe总线为例,信号经历了从第一代产品的2.5 Gb/s速率,到如今主推的第五代32 Gb/s速率,乃至即将发行的第六代64 Gb/s速率的飞速革新[1]。尽管速率提升可以有力推动数字技术发展,却也带来了一系列的困难和挑战,对于SI工程师来说,如何在高度集成的复杂电子系统中保证高速信号质量,完成信号完整性设计,成为了越来越突出的重难点问题。

    所谓信号完整性设计,就是要对引起高速信号失真的各种因素进行优化,尽量减少信号失真,保证其能准确传递信息。引起信号失真的因素主要包括信号网络之间产生的串扰问题,以及信号自身传输媒介引起的反射和损耗问题[2]。因为传输路径存在等效串联和并联电阻,信号在此媒介中传输时必然会有一定的能量损耗,通常高频分量损耗比低频分量大,导致了信号上升边退化现象,引起符号间干扰(ISI)和眼图塌陷等一系列问题[3]。新一代服务器产品中,PCIe Gen5信号速率高达32 Gb/s,损耗引起的上升边退化问题尤为严重,必须进行优化设计。




本文详细内容请下载:http://www.chinaaet.com/resource/share/2000004433




作者信息:

刘  涛,宗艳艳,王乾辉,秦玉倩,田民政,余华国

(浪潮电子信息产业股份有限公司,山东 济南250101)




wd.jpg

此内容为AET网站原创,未经授权禁止转载。