中图分类号：TN402 文献标志码：A DOI: 10.16157/j.issn.0258-7998.239804 中文引用格式： 崔震，周立阳，刘萌，等. 基于FCM flow的小规模数字电路芯片测试[J]. 电子技术应用，2023，49(8)：24-29. 英文引用格式： Cui Zhen，Zhou Liyang，Liu Meng，et al. Small-scale digital circuit chip testing based on FCM flow[J]. Application of Electronic Technique，2023，49(8)：24-29.
Small-scale digital circuit chip testing based on FCM flow
Cui Zhen，Zhou Liyang，Liu Meng，Zhao Yu，Wang Xuede
(3PEAK， Shanghai 201210，China)
Abstract： With the advance of the chip process, the scale of digital chips has increased sharply, and the cost of testing has further increased. Advanced DFT technology has been used on large scale SoC chips, including scan path design, JTAG, ATPG (Automatic Test Pattern Generation) and more. However, for some small scale integrated circuits (analog front end chips for example), inserting test circuits, such as scan chains, will increase chip area and add additional power consumption. For this kind of chip, the test pattern generated from functional simulation cases can be used to detect the manufacturing defects and failures. Therefore, there should be some methodology to verify if the coverage has met the goal, especially for automotive chips.Cadence Verisium Manage Safety Client, relying on core engines of Xcelium Fault Simulator and the Jasper Functional Safety Verification App (FSV) can solve this problem. It provides a credible coverage for ATE (Automated Test Equipment) pattern.
Key words : DFT；coverage；Verisium manager；Xcelium fault simulator；Jasper
