中图分类号：TN402 文献标志码：A DOI: 10.16157/j.issn.0258-7998.256504
中文引用格式： 王淑芬，李应利，高凯菲. 亿门级层次化物理设计时钟树的研究[J]. 电子技术应用，2025，51(9)：35-38.
英文引用格式： Wang Shufen，Li Yingli，Gao Kaifei. Research on billion-gate hierarchical physical design clock tree[J]. Application of Electronic Technique，2025，51(9)：35-38.

Research on billion-gate hierarchical physical design clock tree

Abstract： The traditional spreading physical design can no longer meet the needs of VLSI physical design, and hierarchical physical design has become the mainstream method of VLSI design. In the process of VLSI hierarchical physical design, the clock tree has a great impact on the overall chip timing convergence. Regarding the issue where the billion-gate hierarchical physical design clock tree cannot read the clock tree delay in the submodule, causing significant actual clock deviation, a solution has been proposed to set the actual clock delay of the submodules during the top-level clock tree ccopt phase. This approach effectively reduces clock deviations, thereby providing a solid foundation for subsequent timing optimizations.

Key words : billion-gate；VLSI；hierarchical physical design；clock tree；timing closure