中图分类号：TN432 文献标志码：A DOI: 10.16157/j.issn.0258-7998.256700
中文引用格式： 俞阳，张镇，尤飞龙，等. 1.75 GHz多功能时钟扇出缓冲器设计[J]. 电子技术应用，2025，51(12)：39-43.
英文引用格式： Yu Yang，Zhang Zhen，You Feilong，et al. Design of 1.75 GHz multifunctional clock fanout buffer[J]. Application of Electronic Technique，2025，51(12)：39-43.

Design of 1.75 GHz multifunctional clock fanout buffer

Abstract： A multifunctional clock fan out buffer was designed based on CMOS technology. The buffer is equipped with a programmable frequency divider and delay adjuster, which can independently output differential clocks in 4 channels. Each channel can be divided and delayed for adjustment, and all support three logic level types: LVDS (MAX 1.75 GHz), HSTL (MAX 1.75 GHz), and 1.8 V CMOS (MAX 350 MHz). The testing results show-that: 1.75 GHz differential clock input/output; each output can bypass the frequency divider or set an integer division ratio of up to 2 048; each channel can be adjusted for both digital and analog delay; broadband random jitter<110 fs RMS; additional random jitter of 39 fs RMS (typical value, 12 kHz~20 MHz). It can meet the low jitter requirements for applications such as data converters and clock trees, and can be widely used in wireless transceivers and communication systems.

Key words : clock fanout buffer；divider；delay adjust；additive jitter；CMOS