中图分类号：TP273文献标识码：ADOI:10.19339/j.issn.1674-2583.2026.02.007
中文引用格式：黄俭平，赖宇航，郭彤. 基于国产化FPGA的智能变电站合并单元同步采样系统研究［J］.集成电路应用，2026，43（2）：34-37.
英文引用格式：Huang Jianping, Lai Yuhang, Guo Tong. Research on a synchronous sampling system for smart substation merging units based on domestic FPGA［J］.Application of IC，2026，43（2）：34-37.

Research on a synchronous sampling system for smart substation merging units based on domestic FPGA

Abstract： In order to enhance the autonomous controllability of key equipment in smart substations and to address the engineering requirements of high-precision time synchronization as well as multi-channel synchronous sampling in merging units, this paper investigates a synchronous sampling system based on domestically developed FPGA devices. A system architecture for the merging unit is established using a domestic FPGA platform, incorporating sampling control logic, a time synchronization module, and an SV frame encapsulation mechanism. A multi-clock domain management scheme and data alignment strategy are developed, and experimental validation of synchronization accuracy and real-time performance is carried out. The results indicate that the proposed system meets application requirements in terms of sampling consistency, timestamp accuracy, and network transmission stability in smart substations. The study confirms the engineering feasibility of domestic FPGAs in high-reliability power secondary equipment and provides technical support for core chip localization and the independent development of key smart substation devices.

Key words : domestic FPGA; smart substation; merging unit; synchronous sampling