VHDL编程系列之IEEE STANDARD VHDLAET-电子技术应用-最丰富的电子设计资源平台

VHDL编程系列之IEEE STANDARD VHDL
所属分类：教程\|讲义
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文档大小：1492 K
标签：软件
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文档介绍：VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine read- able and human readable, it supports the development, verification, synthesis, and testing of hard- ware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the lan- guage and the advanced users of the language.
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